Compared with the circuit presented in HDL Example 8.8, a more efficient circuit that co...

Compared with the circuit presented in HDL Example 8.8, a more efficient circuit that counts the number of ones in a data word is described by the block diagram and the partially completed ASMD chart in Fig. P8.37. This circuit accomplishes addition and shifting in the same clock cycle and adds the LSB of the data register to the counter register at every clock cycle.

(a) Complete the ASMD chart.

(b) Using the ASMD chart, write an RTL description of the circuit. A top-level Verilog module, Count_of_ones_2_Beh is to instantiate separate modules for the datapath and control units.

(c) Design the control logic, using one flip-flop per state (a one-hot assignment). List the input equations for the flip-flops.

(d) Write the HDL structural description of the circuit, using the controller designed in part (c) and the block diagram of Fig. P8.37 (a).

(e) Write a test bench to test the circuit. Simulate the circuit to verify the operation described in both the RTL and the structural programs.