Consider the following always block:
always @ ( posedge CLK)
if (S1) R1 <= R1 + R2;
else if (S2) R1 <= R1 + 1;
else R1 <= R1;
Using a four-bit counter with parallel load for R1 (as in Fig. 6.15) and a four-bit adder, draw a block diagram showing the connections of components and control signals for a possible synthesis of the block.
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