The sequential binary multiplier described by the ASMD chart in Fig. 8.15 does not consi...

The sequential binary multiplier described by the ASMD chart in Fig. 8.15 does not consider whether the multiplicand or the shifted multiplier is 0. Therefore, it executes for a fixed number of clock cycles, independently of the data.

(a) Develop an ASMD chart for a more efficient multiplier that will terminate execution as soon as either word is found to be zero.

(b) Write an HDL description of the circuit. The controller and datapath are to be encapsulated in separate Verilog modules.

(c) Write a test plan and a test bench, and verify the circuit.