Repeat Exercise in a process with a lower ratio of diffusion to gate capacitance in which pinv = 0.75. By what percentage does this change the NAND gate delay, as measured in FO4 inverter delays? What if pinv = 1.25?
Exercise
Some designers define a “gate delay” to be a fanout-of-3 2-input NAND gate rather than a fanout-of-4 inverter. Using Logical Effort, estimate the delay of a fanout-of- 3 2-input NAND gate. Express your result both in τ and in FO4 inverter delays, assuming pinv = 1.
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