The clock buffer from Exercise is an example of a 1–2 fork. In general, if a 1–2 fork has a maximum input capacitance of C1 and each of the two legs drives a load of C2, what should the capacitance of each inverter be and how fast will the circuit operate? Express your answer in terms of pinv.
Exercise
The clock buffer in Figure can present a maximum input capacitance of 100 fF. Both true and complementary outputs must drive loads of 300 fF. Compute the input capacitance of each inverter to minimize the worst-case delay from input to either output. What is this delay, in τ ? Assume the inverter parasitic delay is 1.
FIGURE : Clock buffer
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