Problem

The clock buffer in Figure can present a maximum input capacitance of 100 fF. Both true an...

The clock buffer in Figure can present a maximum input capacitance of 100 fF. Both true and complementary outputs must drive loads of 300 fF. Compute the input capacitance of each inverter to minimize the worst-case delay from input to either output. What is this delay, in τ ? Assume the inverter parasitic delay is 1.

FIGURE : Clock buffer

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Solutions For Problems in Chapter 4