Repeat Exercises 1 and 2 using an 8-bit input N7-N0, and realize the circuit using an ABEL program for a single PAL22V10.
Exercise 1Design a clocked synchronous circuit with four inputs, N3, N2, Nl, and N0, that represent an integer TV in the range 0-15. The circuit has a single output Z that is asserted for exactly n clock ticks during any 16-tick interval (assuming that n is held constant during the interval of observation). (Hints: Use combinational logic with a 74x163 set. up as a free-running divide-by-16 counter. The ticks in which Z is asserted should be spaced as evenly as possible, that is, every second tick when n = 8, every fourth when n = 4, and so on.)
Exercise 2Modify the circuit of Exercise so that Z produces N transitions in each 16-tick interval. The resulting circuit is called a binary rate multiplier and was once sold as a TTL MSI part, the 7497. (Hint: Gate the clock with the level output of the previous circuit.)
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