Using the maximum clock frequency determined in Exercise, and assuming an asynchronous tra...

Using the maximum clock frequency determined in Exercise, and assuming an asynchronous transition rate of 4 MHz, determine the synchronizer’s MTBF.

Exercise

The circuit in Figure includes a deskewing flip-flop so that the synchronized output from the multiple-cycle synchronizer is available as soon as possible after the edge of CLOCK. Ignoring metastability considerations, what is the maximum frequency of CLOCK? For a 74AC74, tsetup = 4.5 ns and tpd = 10.5 ns.