Show all steps of your solutions. Attach screen shots of your Logisim Solutions. Solutions without clear...
please solve the question completely and show the steps ... thumb up will be given (5 points each) [CO: 6] a. If RO and R1 are both 16-bit serial shift registers, each with a single serial input (S_IN) and a single serial output (S_OUT), clock and reset. Design using RO and Rl additional logic, a circuit that would store the output S_OUT of either RO or Rl into a D-FF based on input CH. If CH is 0, S OUT...
This section gives you freedom to come up with your own solutions. An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and arithmetic micro-operations on a pair of 4-bit operands. The operations performed by an ALU are controlled by a set of function-select inputs. In this lab you will design a 4-bit ALU with 3 function-select inputs: Mode M, Select S1 and S0 inputs. The mode input M selects between a Logic (M=0) and Arithmetic (M=1)...
all please Design a 3-bit counter that has only one input, w. It counts down 7, 6,5,... 0, 7,.. whenever w-0, and counts up 0,1,2...7,0... when w 1 The output z-1, when the state of the counter is a prime number. Otherwise, z-0 1. List Inputs, Outputs and the count sequence. (5pts) 2. Draw the finite State machine for the counter. (10pts) 3. Draw the state transition table <extra columns for the flip flops values> (20pts) armed resource/content/1/case%20study.template.docx 4. Design...
WITHOUT using VHDL coding, Design the arithmetic unit by showing the truth tables, expressions and the logic circuits! How would I also implement the status flags (Z,C,V) in my circuit? S2 0 1 1. Design a 4-bit Arithmetic Logic Unit (ALU) according to the following specification. Follow the design shown during the lecture. Notice this table is different, though. A(0:3) B(0:3) S1 So Function (F) 0 0 A+B 0 0 A-B Z ALU 0 0 A-1 0 A +1 0...
please explain the solutions for #3 a.) please show all work and clearly 3. (3 pts) Regarding max-length sequence Feedback Equation LFSRS: a) Sketch a max-length sequence LFSR (with FFs and gate-level combination logic) that circulates at least 8 states. Don't use any X2- X1@XO 2 X3- X1 XO 4 X4 X1 XO more components than necessary. An LFSR table is shown. X5 X2 XO X6 X1 XO 5 6 X7 X3 XO X8- X4 X3 eX2 e XO 7...
Please show process and I will rate faster!!! 2. Design a two-bit up/down binary counter using T-fip-flops that can count in binary from 0 to 3. When the control input x is 0, the circuit counts up and when it is 1, the circuit counts down. (a) Obtain the state table of the two-bit counter (P. S., Input, N. S., Output). (b) Obtain the state diagram. (c) Draw the logic diagram of the circuit.
Finite state machine (FSM) counter design: Gray codes have a useful property in that consecutive numbers differ in only a single bit position. Table 1 lists a 3-bit modulo 8 Gray code representing the numbers 0 to 7. Design a 3-bit modulo 8 Gray code counter FSM. a) First design and sketch a 3-bit modulo 8 Gray code counter FSM with no inputs and three outputs, the 3-bit signal Q2:0. (A modulo N counter counts from 0 to N −...
please show the steps and please make sure the solution readable and clear. please be careful about this. best regards. A combinational circuit with four inputs (A,B,C,D) and one output (Z) is designed as follows using an 8:1 multiplexer. Inputs A, B, C are connected to the select lines S2,S1,S, respectively. Multiplexer has the following values connected to the data inputs: 10.14 =D; 1, is = 0; 12,1 = 1; h 13,1, =D For the circuit given above a) Fill...
5) Decoders: Given the following circuit, S0 and S1 are computed using a 4-2 priority encoder with the priorities indicated on the figure. (hint: IDLE signal is always 0, if any of the inputs 10,11,12, or 13 is 1) 6 points) 4-to-2 Priority Encoder 10 YO YI 13 IDLE 13> 11 > 12>10 12 Full c Adder So Fill the following table showing the output signals S0 and SI given the input signals w, x, y, a) and z. Prof...
please answer question 4 (all parts of question4 please) will rate! 3. (30 pts) Design a 2-bit Gray code generator that ropetitively delivers the sequence 00301911-10-00when the input signal UP- 1,or in reverse order 009 10기け01 →00→ when UP-0. Your design should include an asynchronous low. active reset operation: the FSM goes to 00 state when a reset signal is applied In addition to the state output z[1). 2[0]. there is a carry/borrow output bit e which is I when...