Question

Task (10 points): (1) Approach 1: Implement a 4-to-16-line decoder using the schematic capture feature of Xilinx ISE. On the schematic, add a text that clearly shows your name and eRaider ID. (2) Approach 2: Write and compile a 4-to-16-line decoder Verilog gate-level description. (3) Approach 3: Write and compile a 4-to-16-line decoder Verilog behavioral description. (4) Create an appropriate test file to do an exhaustive test. Exhaust all the possible input codes in 3 the following order: 0000 → 0001 → 0010 → 001 1 → for 20 ns, then change to the next input code. → 111 1 . For each input code, hold (5) Run simulation and generate output waveforms for all three approaches to demonstrate that your design works correctly. Be careful about your design to make sure each output is appropriate for the input. Report: Turn in these hardcopy sheets: (1) The schematic of your design including your name and eRaider ID embedded on that sheet; (2) Your Verilog Codes (3) Your test files (4) Your waveform printouts

Answer 1

Trui - T a bl e O o 0 0

4x16 Deuo der -

Be havioral Verilog r4x16 dxoder - module V, 4to I6 dec (A, B, (G o, I); input [4: o] A; lnteqer U always @ CA or Bor Cor) begin T b 00 0 000 0 0 0 00 0 0o 0イ en end module