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(a) Write continuous assign statement in Verilog HDL for the output Z described by the below bread board setup. [Note that(b) Write Verilog HDL for circuit in (a) using if-else statements within an always block. (6 points)(c) Write Verilog HDL for circuit in (a) using case statements within an always block. (6 points)

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a 2 Deo Co 2: 3+ (Co) = 8 CC+D) assign. 2=1[40]8) IC (e|v))) (os) assign 2: (B) & (C D ) Truth Toode aludys (8 or C or D) ° ialways @ CB or cor D). begin. case. (B) i 160 : 2 = C+D; 1bi: ?= 0; default: 7=1bx ; end case end.

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