Question

Final Project Requirements BJT Amplifier Design Final Project Requirements: The Final Project for the ELECTRONICS-1 course for, consists of designing a cascaded BJT Amplifier; using 2 stages. The first stage will be the common Emitter (CE) Amplifier, the second stage is the common Collector (CC) Amplifier, as shown in the general diagram below: CE CC The design requirements are described here: The overall amplification (voltage gain) Atatal as given to each student (each student has different total voltage gain Atotal value] - The input source voltage Vsource is an ideal source(Rs0 Ohm) with peak voltage 10 mv, and the source frequency fsource=2K Hz - The load resistance R = 47 kOhms Each student will have different values needed for the design (see page-2): Student Name Student ID Overall voltage gain (with load) 98 You need to make the design with proper calculations and assumptions for some of the missing values. Make sure the load line and the Q-point, usat) all designed properly. There will be theoretical & practical design as shown in the Final Project Report Template & Rubric. The theoretical design will include the calculations and the assumptions in the design. While the practical design will be building the amplifier circuit using multisim software and showing the results. More description of the BJT Amplifier design is provided in the Final Project Report Template & Rubric.

The Final Project for the ELECTRONICS-1 course for, consists of designing a cascaded BJT Amplifier; using 2 stages. The first stage will be the Common Emitter (CE) Amplifier, the second stage is the Common Collector (CC) Amplifier, as shown in the general diagram below:

The overall amplification (voltage gain) A_{total = 98}

The input source voltage V_source is an ideal source(Rs=0 Ohm) with peak voltage 10 mV, and the source frequency f_source =2K Hz

The load resistance R_L = 47 KOhms

You need to make the design with proper calculations and assumptions for some of the missing values. Make sure the load line and the Q-point, I_c(sat) all designed properly.

Answer 1

If you have any doubt ask in the comment section below.

peak Voltage = 10mv. Given Requirements Av input frequency RL 4762 - 98 2K HZ Circuit Diagram: Vcc=150 Vcc =15V 2 2N2222 A C3 G RB ovo 2N2222A + 1 REZ R347k CE VEE =15V B~200 for 2N2222A Transistof Vcc =150, -VEC =-15V.

First, I design cc then CE Let TE 102 Vee -UBE Rez + RB +1 Iez 15V -0.7V RE + RB BA) REZ = 14,3V = 14.3K_12 + RB 3+1 IMA Let R8 = look a Ro 100 Kn 50052 BH 201 - 50022 REZ - 14.3k_12 REZ 13.8K22 Voltage gain for cc stage is Auz = 9mz (Real Re) (+9m2 (Rezila)

Ima MA Icz V2 - 4omalu 25m v REZIRL 13,8K21 476_12 Real Re 10.67K 2 Ava 4om (10.67K e) 1 + (40m x 10.67K ) Av2 O. 9976 V/v Av AVI x Auz

Avi Av 98 Ave 0.9976 Avi 98.23

Now We design for CE stage. Let IEI =IMA Let Ri=R2 = 100k 22 Rth Rill R2 = LOOK 2 Cook_2 11100k-2 Rin - 50K 2

Rih Bt - Sok 250-12 200+1 Vih 15V x 100k - Vcc 8 R2 R1+R2 100K + 100K Vih = 7.5 V JE, Vih - UBEI REI + Rih B+! 7.5V 0.7V IMA REI +250/2 REI +250R 6.8K R REI 6.55 KB lavil gm, (RC ll Ro) - Comalu gm, Ici Vy IMA asmu

uom (RC look) 9813 99.23 Rellrook Gom Rc lllook 2.46K 2 Rc r 100K = 2.46 K.2 Rc tlook look Rc 2046K Rct +(246x105) 246810 97.54 KRC 11 RC = 246810f = 97.54 K [Rea 2.52K1

Let the Lower cut-off frequency f - 100 HZ ci In the lake Ralcci =Rth = 50k 2 ci = 21TX 100 x 50k = 31.8317 J

Rak = G 21if, Rale Ret Rg C₂ - 21 x 100 (RC +RB) u W 21T X100x (2.52K +100K) 15.52nF = ()

Cz 2TfL (Rake (3) 11 21 x 100 x (RETRL) 21TX 100 X 60.8K C3 26.170F CE 2TfL Raic Ce Rale CE Rh REI Ille tres BHI rei VT IG, 25m v =251 IMA

Ralc Ce 6.55k (250 +25) Raic CE 264 2 CE 11 2T X100x264 CE 6 MF