(a.) The truth table is as follows:-
Q8 | Q4 | Q2 | Q1 | Q8 | Q4 | Q2 | Q1 | Y | m | TQ8 | TQ4 | TQ2 | TQ1 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Q8'Q4'Q2'Q1' | 0 | 0 | 0 | 1 |
0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Q8'Q4'Q2'Q1 | 0 | 0 | 1 | 1 |
0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | Q8'Q4'Q2Q1' | 0 | 0 | 0 | 1 |
0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | Q8'Q4'Q2Q1 | 0 | 1 | 1 | 1 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | Q8'Q4Q2'Q1' | 0 | 0 | 0 | 1 |
0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | Q8'Q4Q2'Q1 | 0 | 0 | 1 | 1 |
0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | Q8'Q4Q2Q1' | 0 | 0 | 0 | 1 |
0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | Q8'Q4Q2Q1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | Q8Q4'Q2'Q1' | 0 | 0 | 0 | 1 |
1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Q8Q4'Q2'Q1 | 1 | 0 | 0 | 1 |
BCD supports only input combinations from 0 to 9, but the possible combinations of 4 variables is 16, therefore the next state for rest of the combinations (10-15) will be don't care.
(b.) The input equations for TQ4, TQ2, TQ1 are as follows:-
(c.) The equation of output signal Y is as follows:-
Problem 2 Design a BCD counter that uses four(4) T flip-flops using the given table format...
Problem 2 Design a BCD counter that uses four(4) T flip-flops using the given table format below. The output signal Y = 0 only during the counter transition from 1001 to 0000, otherwise, Y = 1 (for each valid input). Determine the following: (a) The circuit's state table 14 pts. Present State Next State Output Minterm Flip-Flop Inputs Q8 Q4 Q2 Q1 Q8Q4Q2 Y (m) TQ8 TQ4 TQ2 TQ1 Q1 Required format of the state table in Problem 2(a). Show...
Design a BCD counter that uses four(4) T flip-flops using the given table format below. The output signal Y = 0 only during the counter transition from 1001 to 0000, otherwise, Y = 1 (for each valid input). Determine the following: (a) The circuit's state table Present State Next State Output Minterm Flip-Flop Inputs Q. Q4 Q1 Q: Q4 Q2 Q1 Y (m) T24 T02 TQ1 T08 Required format of the state table in Problem 2(a). Show table grid lines...
Design a BCD counter with four T flip-flops. - The state table should have the present state, next state, output, minterm, and flip-flop inputs. The output signal Y = 0 only during the counter transition from 1001 to 0000, otherwise, Y = 1 (for each valid input). - The input equation for TQ4, TQ2 and TQ1 in SOP. - The equation of the output signal Y in SOP.
Problem 1. Use S-R flip-flops to design a 3-bit counter (C, B, A) with the repeating binary counting sequence: 1, 3, 2, 6, 7, 5, 4. Show clearly the following: (a) The circuit's state table with the present-state entries in ascending order. Present State (t) Next State (t+1) Flip-flop Inputs C B А m C B А Sc Rc SB RB SA RA 14 pts. Required format of the state table in Problem 1(a). Show table grid lines and align...
Problem 1. Use S-R flip-flops to design a 3-bit counter (C, B, A) with the repeating binary counting sequence: 1, 3, 2, 6, 7, 5, 4. Show clearly the following: (a) The circuit's state table with the present-state entries in ascending order. 14 pts. Present State (t) Next State (t+1) Flip-flop Inputs с в А m C B A Sc Rc RE RA SB SA Required format of the state table in Problem 1(a). Show table grid lines and align...
Use S-R flip-flops to design a 3-bit counter (C, B, A) with the repeating binary counting sequence: 1, 3, 2, 6, 7, 5, 4. Show clearly the following: (a) The circuit's state table with the present-state entries in ascending order. Present State (t) Next State (t+1) Flip-flop Inputs с B A m с B A Sc Rc SB RE SA RA Required format of the state table in Problem 1(a). Show table grid lines and align all entries per column....
(a) Design an asynchronous Binary Coded Decimal (BCD) count-up counter using JK flip-flops. Draw the counter circuit clearly showing the configuration of the JK flip-flops and the necessary logic gate(s). Sketch the input and output waveforms of this counter (7 Marks) (b) The binary up/down counter for a cargo lift controller in a 7-storey building has an up-down (UID) control input and a buzzer output (B). The buzzer will sound B 1) when the lift is at level 1 or...
Using S-R flip-flops, design a 3-bit counter (C,B,A) with the repeating binary counting sequence: 1, 3, 2, 6, 7, 5, 4. - Show the circuit's state table with the present-state entries in ascending order, which should have the present state (t), next state (t+1), and flip-flop inputs. - Find the flip-flop input equations for RC, RB, and RA in Product of Sums form.
Please design a 4 bit synchrous counter (0-9 count) using t flip flops. Counter should reset to 0 after 9. Kindly provide all steps including state table. I will be thankful to you.
Design an up/down counter with four states (0, 1, 2, 3) using clocked J-K flip-flops. A control signal x is used as follows: When x 0 the machine counts forward (up), when x , backward (down). Simulate using MultiSim and attach a simulation printout X Please address the following in your report 1. State Table 2. State Diagram 3. Flip-Flop Excitation Tables 4 K-Map Simplification and resulting diagram 5. Multisim Simulation 6. Conclusion/Discussion 7. References Design an up/down counter with...