Question

4. Suppose the MIPS code below is running on the pipeline processor we introduced in the course: Original code: Reordered code: 11: Jw $50, $a0(4) 12: sub $s1, $50, $s3 13: add $81, $si, $s2 14: lw $t1, $a0(8) 15: Jw $t2, $a0(12) 16: add $s3, $t1, $t2 a) List all Read-After-Write (RAW) dependencies in the code. Highlight them over the code above. b) Assume there is no forwarding hardware capability available. How many cycles it takes to run the whole sequence? How many stall occurred? Draw Multiple-clock cycle pipeline diagram and show the stalls. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 11 IF EX M W 12 ID IS 14 15 16 c) Assume there is no forwarding hardware available. Use reordering to minimize stalls you found in b. Draw Multiple-clock cycle pipeline diagram and show the stalls for this new code.

Answer 1

Read After write Hazard $50, II $S1 Iz Iz $t1 → Iz Iy → Is I5 $123 > I6 NO forwarding 5 3 15 6 2 7 16 8 u 9 12 10 13 14 Il If ID EX Me WB I IF X X IDEX mem WB IS ID EX Imem WB I4 IF X Х XIX IF xxx IF XIX quix ID EX mem wol I5 1 XXID EX memwB I 6 IF X X X X X ID EX mem WB Total stalls = 6 Total clocks = 16 © Reordeling Il Iw I2 in Iz: lw $50, $20 (4) #t , $ao (6) $12, $90 (12) $51, $so, $50, $53 $5), $51 $52 $53, $t1, $tz Iy: sub "Is: add 16: add 2 3 4 5 6 7 819 ID 12 13 Ily I) IF ID EX I mem WB I 2 IF ID EX mem | WB IS IF ID EXlmem WB I4 IF ID EX men wB I5 IF X X IS EX Mem/WB IG IF X X IDI EX meml WB stall s=2 Total clock=12

d Forwarding 2 3 4 5 7 9 NI À 10.1.11 12 13 H IFI ID EX mem WB Iz IF ID EX meml WB I 3 IF ID EX mem WB 14 IF ID EX meml WB I5 IF ID EXmcml WB IG IF ID | EX meml wo → Data forwarding Total st alls =D Total clock = 10