7.- Mention 5 different peripherals that a PIC18F45K50 has. 8.- Mention 3 different types of microprocessors...
7.- Mention 5 different peripherals that a PIC18F45K50 has.
8.- Mention 3 different types of microprocessors have existed or exist.
9.- Mention the name and explain the use of the three memory areas of a PIC18F45K50. What capacity (number of words and word width) is each?
10.- Draw the diagram to blocks from a ROM and explain the function of each one. If the memory has a capacity of 8Kx8, how many lines and how many columns does it have?
Homework Answers
7. PIC18F45K50 is a 8-bit microcontroller of PIC18. Five peripherals are:
a. Flash program memory
b.Universal serial port 2.0 module
c. 256 bytes EEPROM
d. 220 bytes SRAM
e. Temperature indicator module
Answer to Q 8.
Three processors belonging to different company are:
1. Intel's existing microprocessor named as Intel Core i7-6950X Processor Extreme Edition (25M Cache, up to 3.50 GHz)
2. AMD A8-9600 Quad-core (4 Core) 3.10 GHz Processor
3. iMAC core i7 2.8 GHz (existed in 2009)
Add Answer to:
7.- Mention 5 different peripherals that a PIC18F45K50 has.
8.- Mention 3 different types of microprocessors...
Consider a read only memory (ROM) with the following specifications: • 256 words • 8 bits...
Consider a read only memory (ROM) with the following specifications: • 256 words • 8 bits per word (a) How many address lines does the memory have? (b) How many data lines does the memory have? (c) If the memory retains its data when power is turned off, is the memory volatile or non-volatile? (d) Identify two types of read only memory (ROM).
8. Draw a diagram of the CUDA device memory model for programmers for the allocation, movement, a...
8. Draw a diagram of the CUDA device memory model for programmers for the allocation, movement, and usage of the various memory types of a device. Explain how CUDA API cudaMemcpy0 functions as data transfer between memories with all its arguments You have to create 6 blocks and every block should contain 8 threads. With the help of a block diagram show how you can create this using 2D Grid of 3D Block. Also mention blockId of each block and...
Plz answers them perfectly as soon as u can We intend to do the address decoding...
Plz answers them perfectly as soon as u can
We intend to do the address decoding of a system whose microcontroller has 20 address lines (A_0 to A_19) and 8 data lines (D_0 to D_7), that it should access ROM and RAM memories, and interface to an LCD Given the information below: ROM 1 2732. initial address Ok RAM 2 6164. immediately after the ROM LCD uses 4 positions, starting at 60K draw its map memory make its address table...
3. Memory organization: Consider 8 Mb SRAM chips with two different internal organizations, 8-bits and 16-bits...
3. Memory organization: Consider 8 Mb SRAM chips with two different internal organizations, 8-bits and 16-bits wide. Show how each of these chips would be inter- connected (rows x columns) to construct a 32 MB memory with the following word a. 16-bit words widths: b. 32-bit words
This question investigates cache use in different types of cache. Consider a system of 8Kbytes of...
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Question 3 The access time of a cache is 80 ns and the access time of...
Question 3 The access time of a cache is 80 ns and the access time of main memory is 1200 ns. We have 85% of instructions are directed to read while 15% is for writes. Hit ratio is 92%. A write through procedure is used. A. Give the average access time considering only the read requests B. Give average access time for both read and write requests. C. Give the overall hit ratio given the write cycle as well. Question...
Let’s say that we have a 4-way set associative cache. The cache has 16 sets in...
Let’s say that we have a 4-way set associative cache. The cache
has 16 sets in total. Main memory consists of 16K blocks of 16
words each, and word addressing is used. a. Show the address format
that is used to map main memory address to the cache. Include the
appropriate fields and their sizes. For the remaining questions,
assume that we have the following situation: We have a program that
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2. (15 points total, 3 pts each) Let’s say that we have a 4-way set associative...
2. (15 points total, 3 pts each) Let’s say that we have a 4-way set associative cache. The cache has 16 sets in total. Main memory consists of 16K blocks of 16 words each, and word addressing is used. a. Show the address format that is used to map main memory address to the cache. Include the appropriate fields and their sizes. For the remaining questions, assume that we have the following situation: We have a program that loops 6...
5. Beta-lactam antibiotics are the major antibiotics. Where they act? Name two different types of antibiotics...
5. Beta-lactam antibiotics are the major antibiotics. Where they act? Name two different types of antibiotics which fall in this category. Explain where they resemble and where they differ. 6. Penicillin and Tetracycline; which one is narrow spectrum and which one is broad spectrum and why-explain. 7. There are two types of antibiotics which act on membrane. Name one member of each type. Why one antibiotics of this group exclusive works on fungus/protists and not on bacteria. 8. Many antibiotics...
Let's start with a memory system that is byte addressable and has 14-bit addresses. Now let's...
Let's start with a memory system that is byte addressable and has 14-bit addresses. Now let's add a direct mapped cache that can hold 16 blocks (or has 16 lines) and each block is 4 bytes. The table shoun below details the contents of the cache at a particular point in time. if the valid bit is 1 there is a cache block loaded into the cache with Tag as detailed in the tag column. The columns B0-D3 then show...
Consider a read only memory (ROM) with the following specifications: • 256 words • 8 bits per word (a) How many address lines does the memory have? (b) How many data lines does the memory have? (c) If the memory retains its data when power is turned off, is the memory volatile or non-volatile? (d) Identify two types of read only memory (ROM).
8. Draw a diagram of the CUDA device memory model for programmers for the allocation, movement, and usage of the various memory types of a device. Explain how CUDA API cudaMemcpy0 functions as data transfer between memories with all its arguments You have to create 6 blocks and every block should contain 8 threads. With the help of a block diagram show how you can create this using 2D Grid of 3D Block. Also mention blockId of each block and...
Plz answers them perfectly as soon as u can
We intend to do the address decoding of a system whose microcontroller has 20 address lines (A_0 to A_19) and 8 data lines (D_0 to D_7), that it should access ROM and RAM memories, and interface to an LCD Given the information below: ROM 1 2732. initial address Ok RAM 2 6164. immediately after the ROM LCD uses 4 positions, starting at 60K draw its map memory make its address table...
3. Memory organization: Consider 8 Mb SRAM chips with two different internal organizations, 8-bits and 16-bits wide. Show how each of these chips would be inter- connected (rows x columns) to construct a 32 MB memory with the following word a. 16-bit words widths: b. 32-bit words
Question 3 The access time of a cache is 80 ns and the access time of main memory is 1200 ns. We have 85% of instructions are directed to read while 15% is for writes. Hit ratio is 92%. A write through procedure is used. A. Give the average access time considering only the read requests B. Give average access time for both read and write requests. C. Give the overall hit ratio given the write cycle as well. Question...
Let’s say that we have a 4-way set associative cache. The cache
has 16 sets in total. Main memory consists of 16K blocks of 16
words each, and word addressing is used. a. Show the address format
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Let's start with a memory system that is byte addressable and has 14-bit addresses. Now let's add a direct mapped cache that can hold 16 blocks (or has 16 lines) and each block is 4 bytes. The table shoun below details the contents of the cache at a particular point in time. if the valid bit is 1 there is a cache block loaded into the cache with Tag as detailed in the tag column. The columns B0-D3 then show...
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