Question

Problem #3: Assume you have a 4.332 MHz master clock as an input to your counter, and you need to generate evenly-spaced single-cycle pulses to enable a digital audio circuit at a target rate of 44,100 Hz. How many master clock cycles occur for every output pulse? Show your calculation. a) b) Since the result is fractional, round it to the nearest whole number. Assuming you use a Modulo-N counter to generate the single-cycle pulses, what is the minimum counter size (number of bits) required to count this number of clock cycles? Using the rounded result, what is the actual (achieved) rate of output pulses per second? Show your calculations c)

Answer 1

(a) Number of master clock cycles occuring per output pulse = master frequncy/output frequency=

(b) $number\ of\ cycles\approx. 98=64+32+2=1100010\ (in\ binary)$

$\therefore$ Minimum size of counter required = 7-bit

(c) Actual frequency of ouput = $\frac{master\ frequency}{98}=\frac{4332000}{98}=44204.08 Hz$