Question

14.31 Consider a CMOS inverter fabricated in a 65-nm CMOS process for which Vpp = 1V, V = - = 0.35 V, and u C = 2.54 C = 470 HA/V'. In addition, ex and Q, have L = 65 nm and (WIL), = 1.5. (a) Find W that results in V = V 2. What is the silicon area utilized by the inverter in this case? (b) For the matched case in (a), find the values of Vow, VOL VW, V2, NM, and NM, (c) For the matched case in (a), find the output resistance of the inverter in each of its two states.

Answer 1

Given data: Consider CMOS Invertor, L = 650m, Von = IV, Ven=- Vtp=0.35V Mn Cox = 2. 5p Cox = 470 m Aly? (4)n = 15 (a) In order to find wp. (W =1.5 [Here L = L p = L n = 650ml wn = 1.5 L Wn = 1.5L Wn = 1.5x65 nm un = 97.5 nm From the formula, Mn Cox Hp Cox WP 2.5 (Mpfox) (replet) Wp = 2,5% wn Wp = 2.5x 97.5 nm Wp = 243 75mm cetilized area for the Investor, A = L (WntWp) - 650m (97.5 nm +243.750m) Silicon 650m (341.25 nm) A = 22181.25 nm

(b) For Low-Level Output Voltage VOL=oul for For ideal logic family in Zero For high level output Voltage, VOH = Voo Volt=1 For high level input voltage VIH= 3 (5400-2Vt) VIH = (501) - 2 (0-35)] - 0.5uv VIH=o.suv For Low level input Voltage VIL = 1/2 ( 3V0o + 2 vt) - $ (30)+2 (0:35)) 0.464 VIL = 0.46v

For High input Noise margin. NMH = VOH VIH I-0.54 For Low NMH = 0.466 Input Noise margin NITL = VIL - VOL = 0.46-0 NML = 0.466 Output resistance for the inverter at n side (Low-olpstate) Yon rencox (2) (VPO - Ven) on (470x1ās) (1.5) (1-0-35) von = 2.1862 crefput resistance for the inverter at P Szde (high-olp State) Vpp = MP Cox (hp (Voo-1 Vepl) (410x4c ( 470x106, 1243.758109 2.5 658109 ) (1-1-0-351) Yop = 2-18kr