Question

Design a computer system with an 8-bit address bus, an 8-bit data bus and it uses isolated I/O. It has: 1128 bytes of PROM starting at address 00H (H meaning in hexadecimal) constructed usin ( one 64x8 chip and multiple 32x2 chips; g (2) 96 bytes of RAM constructed 32x4 chips; (3) an output device with a READY signal at address ABH; (4) an input device with a READY signal at address CDH; (5) a bidirectional input/output device with a READY signal at address FEH Please design the computer organization for this system. (Choose an appropriate starting address for the RAM by yourself, and you are required to a decoder (not combination logic) to enable all the memory chips.) Include all enable and load logic. Problem-Part (c): (10%) Show the memory address range (i.e., the first address and the last address) for the 64x8 PROM chip? Show how you get it?

Answer 1

128 bytes of PROM at starting address OOH Using 64 times 8 & 32 times 2 128 bytes = 128 times 8 bits we have 64 times 8 we need another 64 times 8 by using (32 times 2) we get 64 times 8 (2 times 32) times (2 times 4) (32 times 2) times 8 By using 8 (32 times 32)& 1 (64 times 8) we make 128 bytes PROM 128 times 8 128 - Memory locations 2^7 - 7 input lines starting Address 0000000H Ending Address 0111111 \r\n 96 bytes of RAM with 32 times 4 chips 96 times 8 (32 times 3) times (4 times 2) (32 times 4) times 6 we need 6(32 times 4) chips for 96 bytes RAM let starting Address be 4OH To select 96 locations we need 7 input lines 2^6 = 64 2^7 = 128 40 to 4 F - 16 70 to 7F - 16 80 to 8F - 16 90 to 9F - 96

Partc:

The address for 64 byte prom chip be :

It has 64 registers so we need 64 addresses

Let starting address be 00H then ending address will be 3FH (i.e. 16*4=64 . Here 3=4,F=16).

The given address is when 64 byte chip is used 1st in the 128byte chip.

I have used the combination logic only for chipselect purpose.

Kindly upvote if it's helpful for you .