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Problem 3 (20 points) Implement the decoding of binary state 3 and 5 of a 3-bit synchronous counter. Show the entire counter

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Answer #1

Let Q2Q1Q0 be the output of 3-bit binary counter.

then for state 3 (count 3) Q2Q1Q0= 011 => (~Q2)(Q1)(Q0)

and for state 5 (count 5) Q2Q1Q0= 101 => (Q2)(~Q1)(Q0)

then decoding circuit will be as follows:

HIGH EF FF1 FF2 LSB MSB Ja Qo Q. > JK >c JK >C JK K K Ka PIT DI CLK 3 5

and timing diagram for entire 3 bit synchronous counter along with outputs of decoding gates will be as follows:

CLK 1 2 3 4 5 6 7 8 - - Q - Decoupled outputs 3

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