Write a program in assembly language that loads register R2 with the word in memory location which is 10 bytes above the address in R0; and loads register R3 with the word in memory location which is 10 bytes below the address in R1. Your program must compare the two numbers in R2 and R3. If number in R2 is less than or equal to the number in R3 it must add the two numbers and save the result in the memory location pointed to by R4. Otherwise, your program must subtract the number in R3 from R2 and save the result in the memory location pointed to by R5.
Answer:
Assembly Language Code :
.LC0:
.string "Enter three
numbers: "
.LC1:
.string "Largest number:
"
main:
push
rbp
mov rbp, rsp
push
rbx
sub rsp, 40
mov esi, OFFSET FLAT:.LC0
mov edi, OFFSET FLAT:std::cout
call
std::basic_ostream<char, std::char_traits<char> >&
std::operator<< <std::char_traits<char>
>(std::basic_ostream<char, std::char_traits<char>
>&, char const*)
lea rax, [rbp-20]
mov rsi, rax
mov edi, OFFSET FLAT:std::cin
call
std::basic_istream<char, std::char_traits<char>
>::operator>>(float&)
mov rdx, rax
lea rax, [rbp-24]
mov rsi, rax
mov rdi, rdx
call
std::basic_istream<char, std::char_traits<char>
>::operator>>(float&)
mov rdx, rax
lea rax, [rbp-28]
mov rsi, rax
mov rdi, rdx
call
std::basic_istream<char, std::char_traits<char>
>::operator>>(float&)
movss xmm0,
DWORD PTR [rbp-20]
movss xmm1,
DWORD PTR [rbp-24]
ucomiss xmm0, xmm1
jb .L14
movss xmm0,
DWORD PTR [rbp-20]
movss xmm1,
DWORD PTR [rbp-28]
ucomiss xmm0, xmm1
jb .L15
mov ebx, DWORD PTR [rbp-20]
mov esi, OFFSET FLAT:.LC1
mov edi, OFFSET FLAT:std::cout
call
std::basic_ostream<char, std::char_traits<char> >&
std::operator<< <std::char_traits<char>
>(std::basic_ostream<char, std::char_traits<char>
>&, char const*)
mov DWORD PTR [rbp-36], ebx
movss xmm0,
DWORD PTR [rbp-36]
mov rdi, rax
call
std::basic_ostream<char, std::char_traits<char>
>::operator<<(float)
jmp .L7
.L15:
mov ebx, DWORD PTR [rbp-28]
mov esi, OFFSET FLAT:.LC1
mov edi, OFFSET FLAT:std::cout
call
std::basic_ostream<char, std::char_traits<char> >&
std::operator<< <std::char_traits<char>
>(std::basic_ostream<char, std::char_traits<char>
>&, char const*)
mov DWORD PTR [rbp-36], ebx
movss xmm0,
DWORD PTR [rbp-36]
mov rdi, rax
call
std::basic_ostream<char, std::char_traits<char>
>::operator<<(float)
jmp .L7
.L14:
movss xmm0,
DWORD PTR [rbp-24]
movss xmm1,
DWORD PTR [rbp-28]
ucomiss xmm0, xmm1
jb .L16
mov ebx, DWORD PTR [rbp-24]
mov esi, OFFSET FLAT:.LC1
mov edi, OFFSET FLAT:std::cout
call
std::basic_ostream<char, std::char_traits<char> >&
std::operator<< <std::char_traits<char>
>(std::basic_ostream<char, std::char_traits<char>
>&, char const*)
mov DWORD PTR [rbp-36], ebx
movss xmm0,
DWORD PTR [rbp-36]
mov rdi, rax
call
std::basic_ostream<char, std::char_traits<char>
>::operator<<(float)
jmp .L7
.L16:
mov ebx, DWORD PTR [rbp-28]
mov esi, OFFSET FLAT:.LC1
mov edi, OFFSET FLAT:std::cout
call
std::basic_ostream<char, std::char_traits<char> >&
std::operator<< <std::char_traits<char>
>(std::basic_ostream<char, std::char_traits<char>
>&, char const*)
mov DWORD PTR [rbp-36], ebx
movss xmm0,
DWORD PTR [rbp-36]
mov rdi, rax
call
std::basic_ostream<char, std::char_traits<char>
>::operator<<(float)
.L7:
mov eax, 0
add rsp, 40
pop rbx
pop rbp
ret
__static_initialization_and_destruction_0(int, int):
push
rbp
mov rbp, rsp
sub rsp, 16
mov DWORD PTR [rbp-4], edi
mov DWORD PTR [rbp-8], esi
cmp DWORD PTR [rbp-4], 1
jne .L19
cmp DWORD PTR [rbp-8], 65535
jne .L19
mov edi, OFFSET FLAT:std::__ioinit
call
std::ios_base::Init::Init()
mov edx, OFFSET FLAT:__dso_handle
mov esi, OFFSET FLAT:std::__ioinit
mov edi, OFFSET
FLAT:std::ios_base::Init::~Init()
call
__cxa_atexit
.L19:
nop
leave
ret
_GLOBAL__sub_I_main:
push
rbp
mov rbp, rsp
mov esi, 65535
mov edi, 1
call
__static_initialization_and_destruction_0(int, int)
pop rbp
ret
Write a program in assembly language that loads register R2 with the word in memory location...
Section B - ARM Assembly Language (25 marks) An ARM instruction set summary is provided at the end of this paper 1. (5 marks) Consider the following assembly instruction STMFD r13!, (r5-6} Before executing this instruction, registers hold the following values: Register Value Register r9 Value r4 0x00400040 0x00000000 r5 r10 0x11223344 0x00800080 r6 0x55667788 r11 0x10001000 r7 0x99aabbcc r12 0x20002000 r8 exddeeff00 r13 ex40004000 What memory locations are affected after executing the above instruction? In a table, with a...
Assignment 4: Answer the following questions with reference to the assembly program below. Before the code is executed, the initial content of memory and registers is shown in the figure below memory 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 address Use BIG ENDIAN, and 0x2000.0000 0x2000.0001 0x2000.0002 show all steps register 0x2000.0000RO Ox2000.0003 0x2000.0004 0x2000.0005 0xFFFF.FFFF R2 ox2000.0006 0x1234.5678 R3 0x2000.0007 Ox0000.0000 R1 LDRH R1, [R0 , #2]! LDRH R2 , [R0 , #2)! ADD R3, R1, R2 STR...
Consider the following assembly language code:I0: add $R4,$R1,$R0 //ADD R4 = R1 + R0;I1: lw $R1,100($R3) //LDW R1 = MEM[R3 + 100];I2: lw $R9,4,($R1) // LDW R9 = MEM[R1 + 4];I3: add $R3,$R4,$R9 //ADD R3 = R4 + R9;I4: lw $R1,0($R3) //LDW R1 = MEM[R3 + 0];I5: sub $R3,$R1,$R4 //SUB R3 = R1 - R4;I6: and $R9,$R9,$R7 //AND R9 = R9 & R7;I7: sw $R2,100($R4) //STW MEM[R4 + 100] = R2;I8: and $R4,$R2,$R1 //AND R4 = R2 & R1;I9: add...
computer systems!! pls answer soon 2) Determine the content of memory location named RESULT after execution of each of the following codes: Program B TEXT TEXT LDR R1,-NUM LDR RO, A LDR R2.-N LDR RI.R LDR R2.[R2) MUL RO. RI, RO MOV RO, RO LDR R1. C LOOP: LDR R3, [RII. "4 LDR R2, D MULA RO. R1, R2, RO ADDPL Ra, R0, #1 RO, RESULT STR SUBS R2, R2, #1 S: B S BNE LOOP DATA STR R0,-RESULT A:...
ARM assembly language Write the final updated values for each memory and register after the given instruction executes in the space provided.There are multiple parts of this problem. Note Only write the change values if the values didn't change. Leave the updated cell blank. please explain (as simple as possible ) whats going on after the given command is executed . Q.5.4 Bring to class LSL R6, R6, #3 Updated Data Updated Data Memory Address Ox84F0 Ox 841 Ox84F2 Ox843...
Write a program in ARM assembly language that copies each element of array A to consecutive fourth elements of array B, i.e., A[0] to B[0], A[1] to B[3], A[2] to B[7], etc. The array A is 12 elements long, and each element is a number that is 32 bits (1 word) wide. Assume the base address of array A is in register R2, and the base address of array B is in R3.
Change this program in assembly language to loop until it encounters a sentinel value, which is a negative number. The data begins at x3100. Use only one branch command. There will always be at least one positive integer in the list. .ORIG x3000 LEA R1, xFF AND R3, R3, #0 AND R2, R2, #0 ADD R2, R2, #12 BRz #5 LDR R4, R1, #0 ADD R3, R3, R4 ADD R1, R1, #1 ADD R2, R2, #-1 BRnzp #-6 .END
A list of numbers (in hexa) is stored in the memory location range of (0000 – 00FF), we need to subtract $04 from each number of the list. Solve this problem using assembly language, use the Indexed addressing in writing of your program. Store the result of subtracting each number in the same memory location.
The classic five-stage pipeline MIPS architecture is used to execute the code fragments in this problem. Assume the followings: • The architecture fully supports forwarding, • Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle, • Branches are resolved in the third stage of the pipeline and the architecture does not utilize any branch prediction mechanism, • Register R4 is initially 200. L1: lw lw...
help Question 11 The classic five-stage pipeline MIPS architecture is used to execute the code fragments in this problem. Assume the followings: • The architecture fully supports forwarding, • Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle, • Branches are resolved in the third stage of the pipeline and the architecture does not utilize any branch prediction mechanism, • Register R4 is initially 200....