Describe the first two steps the processor takes with every instruction
The first two steps that the processor takes with every instruction are as follows:
Describe the first two steps the processor takes with every instruction
A processor is designed such that the clock of the processor runs at 1 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 10 cycles Arithmetic Instructions 65% 6 cycles Branch instructions 10% 4 cycles (a) Calculate the CPI for the above benchmark. (b) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new...
A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9 cycles to execute. The manufacturer has decided to design a pipelined version of this processor. For this purpose, the instruction cycle has been divided into five stages with the following latencies: Stage 1 – 2.0 ns,Stage 2 – 1.5 ns, Stage 3 – 1.0 ns, Stage 4 – 2.6 ns, Stage 5 – 1.9 ns. Each stage will require an extra 0.4 ns for...
1- (a) What is the instruction set of a processor architecture? (b) Consider two different processor architectures X and Y. Briefly explain how the instruction sets of X and Y compare (are they the same? do they differ?) (c) Is the size—in bits or bytes—of an instruction part of the ISA? 2- (a) Assembly language consists of nothing but bits? True False (b) Machine language consists of nothing but bits? True False
Processor Hardware Design - MIPS Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy $rt, $rs. when op() op(l) Xyzzy Start: PCout, HARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRoutj IRin Zout, PCin, DUMPonop HALT/* Should end here on undecoded op */ Xyzzy: CONST(-1), Yin SELrs, REGout, ALUxor, Zin Zout, SELrt, REGin, JUMP(Start) Given the xyzzy $rt,$rs instruction as defined above, and assuming that a memory...
Why is a specific TRAP instruction needed to implement syscalls (instead of just using the same instruction that is used for regular function calls)? Then describe in detail the steps taken by the processor when it executes the TRAP instruction.
A designer decides to add a fused multiply-add (FMA) instruction to our MIPS processor. The instruction does the following operation on registers: A=A*B+C. What type of instruction format can we use to encode this new instruction? I, J, Need a new format or R
Given 3 different instruction types, A, B and C. Each type-A, B and C instruction takes 30ns, 20ns and 50ns to complete, respectively. An assembly program is written with 20 type-A, 30 type-B and 40 type-C instructions. Assume a single-issue not pipelined processor, how much time (in nano-seconds) is required to complete the execution of this program? Now let us pipeline these instructions based on a cycle time of 10ns. To pipeline these instructions equally and ideally using this cycle...
Energizing the ADD instruction causes the processor to add the contents of Source A to the contents of Source B and place the result in the tag defined in the instruction's field. Source A Destination Source B DESTB The field contains the tag to which the instruction writes the result of the operation. Source A Source B Destination Output
Q.4 [10 points] A processor is designed such that the clock of the processor runs at 2.0 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 8 cycles Arithmetic Instructions 60% 6 cycles Branch instructions 15% 4 cycles (a) (2 points) Calculate the CPI for the above benchmark. (b) (4 points) Suppose the amount of registers are doubled, such that clock cycle time...
Which of the caches/TLBs in a processor are in the critical path of instruction execution? How does this impact on the design of these structures?