Question

section 13.6

let us assume the following worst case latencies for the blocks in our data path, the sum of which yields the execution latency for lw instruction:

instruction access 2 ns

Register read 1 ns

ALU operation 2 ns

Data cache access 2 ns

Register write back 1 ns

total 8 ns

(13.8 Performance of the single-cycle design Discuss the effects of the following changes in the performance results obtained in Section 13.6: a. Reducing the register access time from 1 ns to 0.5 ns b. Improving the ALU latency from 2 ns to 1.5 ns c. Using cache memories with access time of 3 ns instead of 2 ns

Answer 1

Solution:

Taking all the details into consideration, we are creating different illustrations considering the questions asked,

Illustration 1 (According to given details in Section 13.6):-

Instruction Access = 2 ns

Register Read = 1 ns

ALU Operation = 2 ns

Data Cache Access = 2 ns

Register Write Back = 1 ns

Total = 8 ns = Clock Cycle Time

CPI for this Illustration is 1.

Execution Time = CPI * Clock cycle time = 8 * 1 = 8 ns

Illustration 2 (According to given details in Section 13.8 part a):-

Instruction Access = 2 ns

Register Read = 0.5 ns

ALU Operation = 2 ns

Data Cache Access = 2 ns

Register Write Back = 1 ns

Total = 7.5 ns = Clock Cycle Time

CPI for this Illustration is 1.

Execution Time = CPI * Clock cycle time = 7.5 * 1 = 7.5 ns

Conclusion :- Performance with respect to Illustration 1 = Execution Time of Illustration 1 / Execution Time of Illustration 2

= 8 / 7.5 = 1.06667

Thus, the performance of Illustration 2 is faster than Illustration 1 by 1.06667 times.

Illustration 3 (According to given details in Section 13.8 part b):-

Instruction Access = 2 ns

Register Read = 1 ns

ALU Operation = 1.5 ns

Data Cache Access = 2 ns

Register Write Back = 1 ns

Total = 7.5 ns = Clock Cycle Time

CPI for this Illustration is 1.

Execution Time = CPI * Clock cycle time = 7.5 * 1 = 7.5 ns

Conclusion :- Performance with respect to Illustration 1 = Execution Time of Illustration 1 / Execution Time of Illustration 3

= 8 / 7.5 = 1.06667

  Thus, the performance of Illustration 3 is faster than Illustration 1 by 1.06667 times.

Illustration 4 (According to given details in Section 13.8 part c):-

Instruction Access = 2 ns

Register Read = 1 ns

ALU Operation = 2 ns

Data Cache Access = 3 ns

Register Write Back = 1 ns

Total = 9 ns = Clock Cycle Time

CPI for this Illustration is 1.

Execution Time = CPI * Clock cycle time = 9 * 1 = 9 ns

Conclusion :- Performance with respect to Illustration 1 = Execution Time of Illustration 1 / Execution Time of Illustration 4

= 8 / 9 = 0.88889

  Thus, the performance of Illustration 4 is slower than Illustration 1 by 0.88889 times.

Illustration 5 (According to given details in Section 13.8 part a, b, c):-

Instruction Access = 2 ns

Register Read = 0.5 ns

ALU Operation = 1.5 ns

Data Cache Access = 3 ns

Register Write Back = 1 ns

Total = 8 ns = Clock Cycle Time

CPI for this Illustration is 1.

Execution Time = CPI * Clock cycle time = 8 * 1 = 8 ns

Conclusion :- Performance with respect to Illustration 1 = Execution Time of Illustration 1 / Execution Time of Illustration 5

= 8 / 8 = 1

  Thus, the performance of Illustration 5 and Illustration 1 is the same.