Create a circuit using Logisim that implements a memory register capable of storing a 4 bit binary number. You should investigate the different circuits that can be used to store a bit of memory and then utilize the one that meets the following requirements.
Your register circuit must be able to support the inputs detailed in the following diagram:
Each bit of the register circuit must support a data in, a data out, and a control. The control functions such that the data value will only be changed when the control bit is toggled on.
The value in the register must be persistent and can only be changed when the control bit has been toggled.
You should develop and test the 4 bit register using Logisim.
When you have successfully developed a functioning 4 bit register, you should duplicate the circuit and add it to the two inputs of the ALU circuit below. Add a third register to the output of the ALU as well.
Homework Answers
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Create a circuit using Logisim that implements a memory register
capable of storing a 4 bit...
M1 M3 32-bit pgm. ctr. 32-bit adder register unit 4 data in data memory instr. decoder ALU instru...
M1 M3 32-bit pgm. ctr. 32-bit adder register unit 4 data in data memory instr. decoder ALU instruction memory addr. in M2 addr. in data out dst r data out data in offset operation 2. Can the system in the above figure handle multiplication? Why or why not?
M1 M3 32-bit pgm. ctr. 32-bit adder register unit 4 data in data memory instr. decoder ALU instruction memory addr. in M2 addr. in data out dst r data out data in...
First you must create a logic circuit using only basic gates such as AND, OR, NOR,...
First you must create a logic circuit using only basic gates such as AND, OR, NOR, NAND, NOT, etc. to implement an ADDER capable of adding two 4 bit binary numbers. Second you must create a logic circuit using only basic gates such as AND, OR, NOR, NAND, NOT, etc. to implement a Subtractor that is capable of subtracting the second number from the first, by converting the second number into its 2's complement form and then adding the resulting...
Design a 4-bit register using four J-K flip-flops (D4, D3, D2, and D1) with the following...
Design a 4-bit register using four J-K flip-flops (D4, D3, D2, and D1) with the following behaviour. There are two control inputs, M (mode) and L (load). When L and M are both high, data is loaded in parallel from the data inputs A4, A3, A2, and A1. When M is high and L is low, there is a circular left shift of the data in the register. If you can explain the work, that would be great. Really struggling...
Modify the circuit to support a MFCC instruction. MFCC Rd instruction: Move From Condition Codes MFCC copies into the fo...
Modify the circuit to support a MFCC
instruction.
MFCC Rd instruction: Move From Condition Codes
MFCC copies into the four rightmost bits of Rd the values of the
ALU signals Carry (C), Overflow (O), Zero (Z) and Negative (N) as
they were set by the previous R- type instruction. The remaining 28
bits of Rd are set to zero.
Describe the changes and additions needed for the
single-cycle MIPS processor datapath and control to support this
instruction.
Hints:
1) MFCC...
Objective: Creating a register file (memory) using Verilog. The register file is made up of four registers and each...
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Question 4 2 pts Look at the following (incomplete) diagram of the Hack CPU. Look at the wire (an...
Question 4 2 pts Look at the following (incomplete) diagram of the Hack CPU. Look at the wire (and it is a single wire) pointed to by the large red arrovw Where does the signal on this wire come from and what action does this signal trigger? ALU output decode outM instruction inM addresSM reset PC Figure 5.9 Proposed CPU implementation. The diagram shows only data and address paths, namely, wires that carry data and addresses from one place to...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...
please show work. Build a breadboard circuit for a sequential circuit using D flip-flops that implements...
please show work.
Build a breadboard circuit for a sequential circuit using D flip-flops that implements the sequence 0 +2 +3 +0 ... Note that the sequence repeats itself after only three states. • The circuit must implement a single reset switch to ensure being able to start from zero when desired. There is no need to implement a preset switch. • Use So for reset, PA for the clock, L7 for the top bit of the 2-bit number, and...
b. (i) Draw the circuit diagram of a 4-bit shift register using D-flip-flop. (2 marks) (ii)...
b. (i) Draw the circuit diagram of a 4-bit shift register using D-flip-flop. (2 marks) (ii) Supposing the 4-bit data 1011 is to be transfer in a 4-stage shift register using D-flip- flop, right-out the corresponding output of each of the flip-flop after the 6th clock pulses. (4 marks) c. Design a synchronous counter that go through the state 3, 4, 5, 7,8, 9, 10 . (13 marks)
M1 M3 32-bit pgm. ctr. 32-bit adder register unit 4 data in data memory instr. decoder ALU instruction memory addr. in M2 addr. in data out dst r data out data in offset operation 2. Can the system in the above figure handle multiplication? Why or why not?
M1 M3 32-bit pgm. ctr. 32-bit adder register unit 4 data in data memory instr. decoder ALU instruction memory addr. in M2 addr. in data out dst r data out data in...
Modify the circuit to support a MFCC
instruction.
MFCC Rd instruction: Move From Condition Codes
MFCC copies into the four rightmost bits of Rd the values of the
ALU signals Carry (C), Overflow (O), Zero (Z) and Negative (N) as
they were set by the previous R- type instruction. The remaining 28
bits of Rd are set to zero.
Describe the changes and additions needed for the
single-cycle MIPS processor datapath and control to support this
instruction.
Hints:
1) MFCC...
Objective: Creating a register file (memory) using Verilog. The register file is made up of four registers and each register holds one nibble (half a byte, i.e., four bits) 3. Create a D flip-flop AD flip-flop holds 1 bit of data, and it only changes its data when the clock changes. We want a positive edge triggered flip-flop. Design your Verilog D flip-flop, so we will create them now. Enter the 2 to 4 line decoder. We will need two...
Question 4 2 pts Look at the following (incomplete) diagram of the Hack CPU. Look at the wire (and it is a single wire) pointed to by the large red arrovw Where does the signal on this wire come from and what action does this signal trigger? ALU output decode outM instruction inM addresSM reset PC Figure 5.9 Proposed CPU implementation. The diagram shows only data and address paths, namely, wires that carry data and addresses from one place to...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...
please show work.
Build a breadboard circuit for a sequential circuit using D flip-flops that implements the sequence 0 +2 +3 +0 ... Note that the sequence repeats itself after only three states. • The circuit must implement a single reset switch to ensure being able to start from zero when desired. There is no need to implement a preset switch. • Use So for reset, PA for the clock, L7 for the top bit of the 2-bit number, and...
b. (i) Draw the circuit diagram of a 4-bit shift register using D-flip-flop. (2 marks) (ii) Supposing the 4-bit data 1011 is to be transfer in a 4-stage shift register using D-flip- flop, right-out the corresponding output of each of the flip-flop after the 6th clock pulses. (4 marks) c. Design a synchronous counter that go through the state 3, 4, 5, 7,8, 9, 10 . (13 marks)
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