Homework Answers
a) effective cpi= 0.95*1 +0.05*(0.98*10+0.02*60)=0.95+0.05*11=1.50
b) 1.50=p*1+(1-p)*10
10-9*p=1.5
p=8.5/9=0.94444444
1-p=0.05555555
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18.2 Two-level cache performance A processor with two levels of caches has a CPI of 1...
Consider a processor with a CPI of 1.5, excluding memory stalls. The instruction cache has a...
Consider a processor with a CPI of 1.5, excluding memory stalls. The instruction cache has a miss rate of 1.5%, whereas the miss rate of the data cache is 3.5%. The miss penalty of the data cache is 80 cycles. The percentage of load/store instructions within the running programs is 25%. If the CPI of the whole system, including memory stalls, is 2.5, calculate the miss penalty of the instruction cache. Miss penalty of the instruction cache- Cycles.
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instruct...
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instructions require memory data access Assume cache access time of I cycle Assume hit rate 0.90 for instructiens, 0.80 for data Assume miss penalty (time to read memory inte cache and from cache to Processor with cache processor) is 10 cycles >Compare execution times of 100-thousand instructions:
4B,...
In a memory hierarchy organization with three levels of caches and main memory assume that: Cache...
In a memory hierarchy organization with three levels of caches and main memory assume that: Cache Level L1 has access time tc1 = 5ns and hit ratio h1 = 90%, Cache 2 Level L2 has access time tc2 = 15 ns and hit ratio h2 = 80% Cache Level 3 has access time tc3 = 45 and hit ratio h3 = 60% Main memory access time tm = 100 ns. Find average memory access time. You are required to show...
1. Consider a program that can execute with no stalls and a CPI of 1 if...
1. Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 5% of all load instructions suffer from an L1 cache miss, 2% of all load instructions suffer from an L2 cache miss, and 1% of all load instructions suffer from an L3 cache miss (and are serviced by the memory system). An L1 cache miss stalls...
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of...
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of memory address references, given as word addresses (in decimal, the byte-offset bits have been excluded from addresses). 1, 4, 8, 5, 20, 17, 4, 56, 9, 10, 43, 5, 6, 9, 17 For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks (two words per block) and a total size of 8 blocks....
True or False: In general a computer with two levels of cache is expected to have...
True or False: In general a computer with two levels of cache is expected to have higher miss rate than the computer with one level of cache.
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of...
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially...
3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The o...
3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The one in Problem 2 has a miss penalty of 25 cycles. Calculate the total time taken (in cycles) for all accesses, for each cache. Which cache is better- the one in Problem 1 or Problem 2? 3. 12+2-4 points] We are comparing...
(15pts) Answer each of the following with a TRUE (T) or (1) Data in SRAM will...
(15pts) Answer each of the following with a TRUE (T) or (1) Data in SRAM will be lost without refreshing frequently or FALSE (F) 9. (2) A cache is a small fast memory that stores a subset of the informatio (3) In set associative cache, ory block can be placed in only (4) The unit of data transfer between cache and main memory is a w (5) When CPU requests a word and cannot find it in cache, it a...
Exercise 8.16 You are building a computer with a hierarchical memory systenm that consists of separate...
Exercise 8.16 You are building a computer with a hierarchical memory systenm that consists of separate instruction and data caches followed by main memory. You are using the ARM multicycle processor from Figure 7.30 running at 1 GHz (a) Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5% miss rate. On a cache miss, the processor stalls for 60 ns to access main memory, then resumes normal operation. Taking cache misses into account,...
Consider a processor with a CPI of 1.5, excluding memory stalls. The instruction cache has a miss rate of 1.5%, whereas the miss rate of the data cache is 3.5%. The miss penalty of the data cache is 80 cycles. The percentage of load/store instructions within the running programs is 25%. If the CPI of the whole system, including memory stalls, is 2.5, calculate the miss penalty of the instruction cache. Miss penalty of the instruction cache- Cycles.
4B, 20%) compare performance of a Processor with cache vs. without cache. Assume an Ideal processor with 1 cycle memory access, CPI1 Assume main memory access time of 8 cycles Assume 40% instructions require memory data access Assume cache access time of I cycle Assume hit rate 0.90 for instructiens, 0.80 for data Assume miss penalty (time to read memory inte cache and from cache to Processor with cache processor) is 10 cycles >Compare execution times of 100-thousand instructions:
4B,...
In a memory hierarchy organization with three levels of caches and main memory assume that: Cache Level L1 has access time tc1 = 5ns and hit ratio h1 = 90%, Cache 2 Level L2 has access time tc2 = 15 ns and hit ratio h2 = 80% Cache Level 3 has access time tc3 = 45 and hit ratio h3 = 60% Main memory access time tm = 100 ns. Find average memory access time. You are required to show...
1. Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 5% of all load instructions suffer from an L1 cache miss, 2% of all load instructions suffer from an L2 cache miss, and 1% of all load instructions suffer from an L3 cache miss (and are serviced by the memory system). An L1 cache miss stalls...
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of memory address references, given as word addresses (in decimal, the byte-offset bits have been excluded from addresses). 1, 4, 8, 5, 20, 17, 4, 56, 9, 10, 43, 5, 6, 9, 17 For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks (two words per block) and a total size of 8 blocks....
3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The one in Problem 2 has a miss penalty of 25 cycles. Calculate the total time taken (in cycles) for all accesses, for each cache. Which cache is better- the one in Problem 1 or Problem 2? 3. 12+2-4 points] We are comparing...
(15pts) Answer each of the following with a TRUE (T) or (1) Data in SRAM will be lost without refreshing frequently or FALSE (F) 9. (2) A cache is a small fast memory that stores a subset of the informatio (3) In set associative cache, ory block can be placed in only (4) The unit of data transfer between cache and main memory is a w (5) When CPU requests a word and cannot find it in cache, it a...
Exercise 8.16 You are building a computer with a hierarchical memory systenm that consists of separate instruction and data caches followed by main memory. You are using the ARM multicycle processor from Figure 7.30 running at 1 GHz (a) Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5% miss rate. On a cache miss, the processor stalls for 60 ns to access main memory, then resumes normal operation. Taking cache misses into account,...
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