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Design Project #1 : Design of PID Controller Design a PID controller so that the step response of the following closed-loop system satisfy (settling time) 3sec, POS(% overshoot) 20%, and steady state tracking error (ess)<0. R(s) Y(s) K, ss +1 If you can reduce both settling time and overshoot, then it would be much better. To verify your answer, you should use Matlab simulink and show that your answer is correct in your report. Describe the detailed design procedure (as studied in the lecture) and show that your design satisfies the above specification in your report. Also, provide the discussion on your results Submit your Matlab files (!) to e-class. (Caution!!) Do not copy the report or simulation. TA will check it in details and in that case both of you will get zero point
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