a)
I'll refer this table for all that data for part (a).
it means 27% of 29.7% instructions need the data being loaded additionally to the load instructions.
so, all instructions which need data to be loaded is (1+0.27)*0.297
stall cycles in Load = 1.27*0.297*1 = 0.37719
It means 47% of branch instruction need no stall cycles.
and 53% of branch instruction require stall cycles.
therefore,
stall cycles in Branch = 0.53*0.262*2 = 0.27772
Total stalls = 0.37719 + 0.27772 + 0.294 + 0.147 = 1.09591
Avg CPI = CPIideal + stalls = 1 + 1.09591 = 2.09591
CPI = 2.09591
b)
we can see delay is maximum in memory read/write block,
therefore, clock cycle time must be greater than or equal to delay at memory read/write block
which is,
hence, cct = 0.50 nsec
CPUtime = IC * CPI * cct
= (12.3*107 ) * 2.09591 * 0.50 nsec
= 12.88985 * 107 nsec
= 128.8985 msec
A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides...
Computer Architecture
6. We can choose pipelined or non-pipelined implementation like below. For a program with 20% ALU instructions, 10% control instructions and 70% memory instructions, which design will be faster? Give a quantitative CPI average for each case. (you have to write all process like CPI, CPI time, etc) Non-Pipelined version Parameter Clock Rate CPI for ALU instruction CPI for Control instruction 2 CPI for Memory instruction3 Pipelined version 250 MHz 600 MHz
6. We can choose pipelined or...
Consider the following code to be executed on a pipelined processor lw $s1, 40(Ss6) add $s6, $s2, $s2 sw Ss6, 48(Ss1) a. Include stalls/nops in the code so it executes correctly in the cases of (i) No forwarding (ii) ALU-ALU for warding, (iii) Full forwarding b. In each case calculate the number of clock cycles required to execute the code c. Assume further that the clock cycle time is 110 ps with no forwarding, 120 ps with ALU-ALU forwarding and...
Which of the following are true of pipelined datapaths (as opposed to non-pipelined datapaths): Select all that apply The amount of time it takes for an instruction to go through the pipeline is higher because of setup and hold times of latches Clock cycles per instruction generally goes up More control is needed More latches/registers are required Instruction throughput, i.e., number of instructions executed per cycle, generally goes up
A processor is designed such that the clock of the processor runs at 1 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 10 cycles Arithmetic Instructions 65% 6 cycles Branch instructions 10% 4 cycles (a) Calculate the CPI for the above benchmark. (b) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new...
Please help me !!!
You designed a new CPU (not pipelined) that has only 5 instructions. You found that the CPU provides the following performance characteristic in Table 7-1. The CPU is able to run at 800MHz. How many clock cycles does CPU need to run the following assembly code? How much time does CPU need to run the code? What is the average CPI to run the code on the CPU?
Q.4 [10 points] A processor is designed such that the clock of the processor runs at 2.0 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 8 cycles Arithmetic Instructions 60% 6 cycles Branch instructions 15% 4 cycles (a) (2 points) Calculate the CPI for the above benchmark. (b) (4 points) Suppose the amount of registers are doubled, such that clock cycle time...
Given a processor that runs at 1GHz with the following: Instruction-------------- Frequency --------------Cycles Load & store ----------------25% --------------------10 arithmetic instructions------ 65% --------------------6 branch instructions -----------10%-------------------- 4 1) Calculate the CPI for the above. 2) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new clock speed (in GHz)? 3) Assume only the load & stores instructions are speed up by 5 times and their frequency is increased to 50% (Arithmetic instructions...
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A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...