Question

Which of the following are true of pipelined datapaths (as opposed to non-pipelined datapaths): Select all that apply The amount of time it takes for an instruction to go through the pipeline is higher because of setup and hold times of latches Clock cycles per instruction generally goes up More control is needed More latches/registers are required Instruction throughput, i.e., number of instructions executed per cycle, generally goes up

Answer 1

Pipelined Datapath

• The pipelined datapath combines ideas from the single and multicycle processors.
• It uses multiple memories and ALUs.
• Instruction execution is split into several stages.
• Pipeline registers propagate data and control values to later stages.
• The MIPS instruction set architecture supports pipelining with uniform instruction formats and simple addressing modes.
• The goal of pipelining is to allow multiple instructions execute at the same time.
• We may need to perform several operations in a cycle.
• Increment the PC and add registers at the same time.
• Fetch one instruction while another one reads or writes data.
• Thus, like the single-cycle datapath, a pipelined processor needs to duplicate hardware elements that are needed in the same clock cycle.

1 IF lw $t0, 4($sp) sub $v0, $a0, $a1 and $t1, $t2, $t3 or $50, $81, $s2 add $t5, $t6, $0 Clock cycle 2 3 4 5 6 7 8 9 ID EX MEM WB IF | ID | EX MEM| WB | IF ID EX MEM WB IF ID EX MEM WB IF IDEX MEM WB Thus, like the single-cycle datapath, a pipelined processor needs to duplicate hardware elements that are needed in the same clock cycle

PCSrc IF/ID ID/EX EX/MEM MEM/WB RegWrite Shift left 2 ALU Zero Mem Write Read data 1 Read data 2 Read Instruction address [31-0] D Result L Address Read register 1 Read register 2 Write register Write data Data memory Instruction memory Mem ToReg Registers ALUOP ALUSrc Write data Read data Instr [15-] Sign extend) RegDst MemRead Instr [20 - 16] Instr [15 - 11] eo-

CONCLUSION:

1. The amount of time it takes for an instruction to go through the pipeline is higher because of setup and hold times of latches.-True

Explanation:

Pipelining increases the CPU instruction throughput. But it does not reduce the execution time of an individual instruction. In fact, it usually slightly increases the execution time of each instruction due to overhead in the pipeline control.

2. Clock cycles per instruction generally goes up.-False

Explanation:

Since pipelining increases the throughput, or the amount of work done per unit time, several instructions are executed together in a clock cycle.

3. More control is needed.-False

Explanation:

Actually, we need the same number or less. The control signals are generated in the same way as in the single-cycle processor—after an instruction is fetched, the processor decodes it and produces all of the appropriate control values. But just like before, some of the control signals will not be needed until some later stage and clock cycle. These signals must be propagated through the pipeline until they reach the appropriate stage. We can just pass them in the pipeline registers, along with the other data. Control signals can be categorized by the pipeline stage that uses them.

4. More latches/registers are required.-True

Explanation:

Most latches are used to synchronize inputs and outputs since different parts (groups) are processed at different cycles.

5. Instruction throughput, i.e., number of intructions executed per cycle, generally goes up. -True

Explanation:

Pipelining does not improve the execution time of any single instruction. Each instruction here actually takes longer to execute than in a single-cycle datapath (15ns vs. 12ns). Instead, pipelining increases the throughput, or the amount of work done per unit time.

The result is improved execution time for a sequence of instructions, such as an entire program.