Question

Part 1: A pipelined computer completes instructions more quickly by having more than one instruction at a time "in the pipeline." Explain what problem branch instructions cause with instruction pipelining. Describe one approach to overcoming this problem.

Part 2: RISC computers generally execute more instructions per second than CISC computers. Describe the penalty or trade-off paid when adopting the RISC architecture.

Part 3: When a cache hit to a cache on the CPU chip occurs on a memory write the cache will be updated, but the main memory will not be unless the designers of the memory subsystem have taken steps to do so. What effect does a mismatch between cache and main memory have on a computer with two or more CPU chips?

Part 4: Explain why programmed I-O is seldom used for general I-O operations?

Part 5: DMA I-O frees the CPU to do other work while an I-O operation is pending. Using DMA I-O requires more complex controller hardware and more complex bus. In addition, there is an operational penalty; that is, a disadvantage that shows up while a DMA I-O operation is in progress. Explain what it is.

Part 6: Cache memory is faster than main memory, but also much smaller. In general, cache memory is not large enough to hold all of an executing program. In about a paragraph, explain how cache memory is able to speed up the execution of programs. Just naming the principle involved is not enough; you must explain it.

Part 7: When a cache miss occurs on a memory read, the cache controller and memory take three major steps, assuming that the cache has no free cache line when the miss occurs. List and briefly explain each one in the order they occur.

Part 8: Explain what a privileged instruction is. In about a paragraph, explain why privileged instructions are needed in modern computer systems.

Part 9: Name and briefly describe three different uses for interrupts.

Part 10: Explain what a software interrupt is. Name and briefly describe one important application of software interrupts.

Answer 1

Solution

In branch instructions only one instruction is being completed at time.

This causes issues when instructions have different numbers of steps.

Solutions:
using separate pipelines

reordering instructions

requiring that the following instruction not be dependent on the branch.

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There are few kinds of instructions used

More statements are needed = less flexible

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The CPU would look for the data that is mismatched on the L2 cache and if not then found would continue on to the other caches if present.

This allows it to still be quicker than using main memory

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CPU can't do anything while I-O is in process.

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The I-O module steals cycles on the memory bus from the CPU, causing the CPU to wait anyway.

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Locality of reference

most memory references in cache memory are confined to a small region at any given time.

This allows for a program to access this small amount of data that is close together very quickly.

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Send the address and read operation to the next level of the hierarchy.

Wait for the data to arrive

Update the cache entry with data, rewrite the tag,
turn the valid bit on, clean the dirty data

Resend the memory address until you get a hit

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An instruction that only the operating system can execute when in a specific mode.

needed to allow the operating system to perform certain operations that other applications should not be allowed to perform.

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Freeing CPU from waiting for events

Providing control for external input

Notifying that an external event has occurred

Allocating CPU time

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When software instructions causes the CPU to alter its normal flow of instruction execution.

It can free the CPU form waiting for events and provide control for external input.

This could be used to communicate with the operating system
i.e. requesting for input/output.

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