urgent help needed in computer architecture ! Thanx
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Question 4 (9 pts total) program consists of 8 instructions. Each instruction takes an average of...
Part 1: A pipelined computer completes instructions more quickly by having more than one instruction at...
Part 1: A pipelined computer completes instructions more quickly by having more than one instruction at a time "in the pipeline." Explain what problem branch instructions cause with instruction pipelining. Describe one approach to overcoming this problem. Part 2: RISC computers generally execute more instructions per second than CISC computers. Describe the penalty or trade-off paid when adopting the RISC architecture. Part 3: When a cache hit to a cache on the CPU chip occurs on a memory write the...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
1. (4 pt) Circle True or False. Each is 2 pts. t Recently Used (LRU) replacement...
1. (4 pt) Circle True or False. Each is 2 pts. t Recently Used (LRU) replacement policy generates better miss penalty than FIFO for fully- associative caches ngger b me rna 2. (8 pt) Find the Average Memory Access Time (AMAT) for a machine with following configuration: The machine has the hit rate of 95% with the hit time of 2 ns. A miss costs 30 ns to fetch the desired ume that the read and write miss penalties are...
Operating Systems Questions (Please help if you can) 1. A computer has cache, main memory, and...
Operating Systems Questions (Please help if you can) 1. A computer has cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20ns are required to access it. If it is in main memory but not in the cache, 60ns are required to load it into the cache (this includes the time to originally check the cache), and then, the reference is started again. If the word is not in main memory,...
Question 4 (10 pt). One difference between a write-through cache and a write-back cache can be...
Question 4 (10 pt). One difference between a write-through cache and a write-back cache can be in the time it takes to write. During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) we actually write the data. Let’s assume that 50% of the blocks are dirty for a write-back cache. For this question, assume that the write buffer for the write through will never stall the CPU (no penalty). Assume a...
Question 33 10 pts For a direct mapped cache of 4 blocks with a cache block...
Question 33 10 pts For a direct mapped cache of 4 blocks with a cache block size of 1 byte, in which cache block will each memory location map to? The order of accesses if given by the operation number. Indicate if each access is a hit or a miss, and what the tag value is for each entry. Assume that the cache is initially empty, and the accesses are in order of appearance. REDRAW AND COMPLETE THE CACHE TABLE...
Q.. Chocoe the right anwerts .20 points Which one in the right order of datapath thst...
Q.. Chocoe the right anwerts .20 points Which one in the right order of datapath thst an imstcto shld w along b) MEM-ID-EX-IF WB 2 Hazard is a situation that prevents the next instruction to start in nest cycle. If the hazard occurs dae to a required resource which is busy, which hazard tha a) Data Hazard b) Structure Hazard c) Control Hazard d) All of the above 1.3 "Iems accessed roceistly are likely to be accossed again soon instructions...
4. (3 pts. each) Write the hexadecimal representation of each MIPS assembly instruction: (4.1) sub $s3,...
4. (3 pts. each) Write the hexadecimal representation of each MIPS assembly instruction: (4.1) sub $s3, $t1, $s2 (4.2) bne $t3, $t4, 18 (4.3) sll $s0, $t5, 2 5. (20 pts.) Consider the following C (or java) code: else f=f+2; By storing the value of j in Ss0, write a sequence of MIPS assembly instructions that will execute these lines of code for the following two cases: (5.1) assuming that the values of f, g and h are stored in...
2. (15 points total, 3 pts each) Let’s say that we have a 4-way set associative...
2. (15 points total, 3 pts each) Let’s say that we have a 4-way set associative cache. The cache has 16 sets in total. Main memory consists of 16K blocks of 16 words each, and word addressing is used. a. Show the address format that is used to map main memory address to the cache. Include the appropriate fields and their sizes. For the remaining questions, assume that we have the following situation: We have a program that loops 6...
Thank you!!! 4.1 [2 pts. int rollO Define a function roll() that takes no arguments, and...
Thank you!!!
4.1 [2 pts. int rollO Define a function roll() that takes no arguments, and returns a random integer from 1 to 6. Before proceeding further, we recommend you write a short main method to test it out and make sure it gives you the right values. Comment this main out after you are satisfied that roll() works. Remenber:texibook Seciion 49 is on randormness, and Chapier 5is on functions. int getKandomNumber return 4 l chosen by fair dice roll....
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
1. (4 pt) Circle True or False. Each is 2 pts. t Recently Used (LRU) replacement policy generates better miss penalty than FIFO for fully- associative caches ngger b me rna 2. (8 pt) Find the Average Memory Access Time (AMAT) for a machine with following configuration: The machine has the hit rate of 95% with the hit time of 2 ns. A miss costs 30 ns to fetch the desired ume that the read and write miss penalties are...
Question 33 10 pts For a direct mapped cache of 4 blocks with a cache block size of 1 byte, in which cache block will each memory location map to? The order of accesses if given by the operation number. Indicate if each access is a hit or a miss, and what the tag value is for each entry. Assume that the cache is initially empty, and the accesses are in order of appearance. REDRAW AND COMPLETE THE CACHE TABLE...
Q.. Chocoe the right anwerts .20 points Which one in the right order of datapath thst an imstcto shld w along b) MEM-ID-EX-IF WB 2 Hazard is a situation that prevents the next instruction to start in nest cycle. If the hazard occurs dae to a required resource which is busy, which hazard tha a) Data Hazard b) Structure Hazard c) Control Hazard d) All of the above 1.3 "Iems accessed roceistly are likely to be accossed again soon instructions...
4. (3 pts. each) Write the hexadecimal representation of each MIPS assembly instruction: (4.1) sub $s3, $t1, $s2 (4.2) bne $t3, $t4, 18 (4.3) sll $s0, $t5, 2 5. (20 pts.) Consider the following C (or java) code: else f=f+2; By storing the value of j in Ss0, write a sequence of MIPS assembly instructions that will execute these lines of code for the following two cases: (5.1) assuming that the values of f, g and h are stored in...
Thank you!!!
4.1 [2 pts. int rollO Define a function roll() that takes no arguments, and returns a random integer from 1 to 6. Before proceeding further, we recommend you write a short main method to test it out and make sure it gives you the right values. Comment this main out after you are satisfied that roll() works. Remenber:texibook Seciion 49 is on randormness, and Chapier 5is on functions. int getKandomNumber return 4 l chosen by fair dice roll....
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