Question

Write a Verilog model of a circuit whose 8-bit output is formed by shifting its 8-bit input one position to the right and filling the vacant positions with the bit that was in the MSN before the shift occurred (shift arithmetic right). Write a test bench and simulate the circuit. Please Implement the exercises and comments for each line Thank you.

Answer 1

module mod(in,out);
input[7:0] in;
output reg [7:0] out;

always@(in)
begin
out[7]=in[7];
out[6]=in[7];
out[5]=in[6];
out[4]=in[5];
out[3]=in[4];
out[2]=in[3];
out[1]=in[2];
out[0]=in[1];
end
endmodule

module tb;
reg[7:0] rin;
wire[7:0] wout;

mod m1(rin,wout);

initial
begin
rin=8'b10101010;
#5 $display("%b",wout);
end
endmodule