(a) Design an asynchronous Binary Coded Decimal (BCD) count-up counter using JK flip-flops. Draw the counter circuit clearly showing the configuration of the JK flip-flops and the necessary logic gate(s). Sketch the input and output waveforms of this counter (7 Marks) (b) The binary up/down counter for a cargo lift controller in a 7-storey building has an up-down (UID) control input and a buzzer output (B). The buzzer will sound B 1) when the lift is at level 1 or...
2. Synchronous Counters: a. Design a count up/count down counter that counts from 0 up to 4, then 4 down to 0 using D flip flop. b. Design a count up counter that counts from 0 up to 12 using JK flip flops.
It is a question about Computer organization
Design a sequential up/down counter. The counter should count as follows: When x -0, the counter will count 0, 1, 2, 3, 4, 5, 6, 7, 0,... When x 1, the counter will count 7, 6, 5, 4, 3, 2, 1, 0,7, .. 6.1. Draw the state diagram. 6.2. Draw the state table. 6. 6.3. Draw the excitation table using JK flip-flop. 6.4. Minimize. 6.5. Draw the logic diagram of your answer.
Design serial (asynchronous) counter modulo 7 using synchronous flip-flops (T, D or JK). The counter should count up.
Design a two-bit up/down binary counter using D flip-flops that can count in binary from 0 to 7. When the control input x is 0, the circuit counts down, and when it is 1, the circuit counts up. (a) Obtain the state table of the two-bit counter. (b) Obtain the state diagram (c) Draw the logic diagram of the circuit.
Design in VHDL a 4-bit up-down counter as presented below:
The operation of the up-down counter is described by the
following truth table:
S1 S0
Action
0 0
Hold
0 1
Count up
1 0
Count down
1 1
Parallel Load
Provide VHDL code and testbench
XЗ Q3 X3X2X1X0 Parallel Load X2 S1SO Function Select Input Q2 RST-Asynchronous Reset Input X1 CLK- Clock Input Q1 хо Q3Q2Q1Q0 - Parallel Output Q0 CLK S1 S0 RST
XЗ Q3 X3X2X1X0 Parallel Load...
pleas help fast
Problem #3 (30 points) a. Design an Asynchronous Modulo 9 counter (a counter that counts from 0 to 8) using JK Flip-Flops. Sketch the circuit only. (15 pts) b. Design a Synchronous Modulo 9 counter (a counter that counts from 0 to 8) using JK Flip- Flops. Sketch the circuit only. (15 pts)
6. Show how to connect a 74HC93 4-bit asynchronous counter for each of the following moduli: (a) 9 (b) 11 (c) 13 (d) 14 (e) 15 10. The waveforms in Figure 9-69 are applied to the count enable, clear, and clock inputs as indi- cated. Show the counter output waveforms in proper relation to these inputs. The clear input is asynchronous. CTEN CTENCTR DIV 16 CLR
bas Q3) Write a Verilog description of a 4-bit counter with asynchronous reset that has two control inputs Munctionaloyg C1 and CO with the following functionality: 10 marks] CI CO Action 0 0No Change 0 1 Count up by 1 10 Count up by 2 1 1 Count up by 3
to count from O to 4, and again from the zero count in the counter to start, design the counter.
to count from O to 4, and again from the zero count in the counter to start, design the counter.