2. Make an 8-to-1 multiplexer with a 3-to-8 decoder and two groups of 8 AND gates...
2. Make an 8-to-1 multiplexer with a 3-to-8 decoder and two groups of 8 AND gates each, plus an OR gate. The 3-to-8 decoder must be done with hierarchical design and several AND gates. You are strongly advised to use Logic Works 5 or similar circuit design software to create circuit diagrams for this question. For hierarchical design, you can draw over the exported circuit diagram to outline smaller hierarchical parts
Homework Answers
Here is the 8 AND gates are used to route 8 inputs to outputs with the OR gate and all AND gates are connected with 3:8 decoder input with the function truth table.
Add Answer to:
2. Make an 8-to-1 multiplexer with a 3-to-8 decoder and two
groups of 8 AND gates...
Make a 4-to-16 decoder and show its circuit diagram in both ways: -Create every minterm via...
Make a 4-to-16 decoder and show its circuit diagram in both ways: -Create every minterm via multiple 4-input AND gates. -Employ hierarchical design, use smaller decoders and two groups of 8 AND gates.
Design the circuit with a 3-to-8 decoder and external OR gates. 8 Assume we want to...
Design the circuit with a 3-to-8 decoder and external OR gates. 8 Assume we want to implement a function: =Zm(1,2,6,7) (F(X,Y,Z You may label necessary parts of the diagrams with x, X, Y, Y', Z, Z', 1,0, F, etc.. a. Show how to implement the function F using only the decoder below and one additional gate. +5V Q7 EN Q6 Q5 Q4 Q악 Q1 SO
Create a minimal design for a 2-to-1 multiplexer using only NAND gates. Assume that no inverted...
Create a minimal design for a 2-to-1 multiplexer using only NAND gates. Assume that no inverted input signals are available. Do not use any other type of gate. If you need to invert a signal, it must be done using a NAND gate.
3. [20 pts] 8-segment decoder for 8 symbols. Implement (draw logic diagram) the segment 4 of the 8-segment decoder...
3. [20 pts] 8-segment decoder for 8 symbols. Implement (draw logic diagram) the segment 4 of the 8-segment decoder for 8 symbols 0 (a) Using K-map to realize the function q 16 pts) (b) Using a 3-8 decoder and OR gates to realize the function q.[7 pts] (e Using 8-to-1 multiplexer to realize the function 17 pts] Notes: 1. A eight-segment decoder is a combinational circuit with a three-bit input a and a 8-bit output q. Each bit of q...
Design a dual 8-to-1 line multiplexer using a 3-to-8 line decoder and two 8X2 AND-ORS.
Design a dual 8-to-1 line multiplexer using a 3-to-8 line decoder and two 8X2 AND-ORS.
ECE 1552- Summer 2019 Homework 2: Solve all questions. HW is to be turned in as a PDF or word document on canvas. Show...
ECE 1552- Summer 2019 Homework 2: Solve all questions. HW is to be turned in as a PDF or word document on canvas. Show all working. Answers provided should be typed or written CLEARLY 1: Find a function to detect an error in the representation of a decimal digit in BCD. In other words, write an equation with value 1 when the inputs are any one of the six unused bit combinations in the BCD code, and value 0 otherwise...
Draw the schematic of a 2-4 line decoder using basic gates. (xou need to use 7404,...
Draw the schematic of a 2-4 line decoder using basic gates. (xou need to use 7404, 7408 & 7432. For detailed instruction about these ICs refer to Lab HO #3). 1. 2. Write down the IC numbers and pin numbers of the gates in your schematic. 3. Find the Truth Table and Boolean Expression of the circuit 4. 5. Now based on the same design principles comclude a 3-8 line decoder and draw the diagram only (no need for the...
Having the next Boolean functions: F1(x,y,z)-П (1, 3, 5) . F2(x,y,z)-Σ (0, 2, 4, 5) . 1. Make one...
Computer architecture
Having the next Boolean functions: F1(x,y,z)-П (1, 3, 5) . F2(x,y,z)-Σ (0, 2, 4, 5) . 1. Make one logic gate design circuit, using AND, OR and NOT logic gates (20 points). 2. Design two 4-to-1 selectors, one for each Boolean function (20 points) 3. Design one 3-to-8 decoder to solve both Boolean functions (20 points) 4. Design a 8x2 ROM to solve both Boolean functions (20 points) 5. Design a 3x5x2 PLA to solve both Boolean functions...
(a) The truth table below shows a certain function F(P,Q,R,S). Implement the function F using an 8:1 multiplexer, withou...
(a) The truth table below shows a certain function
F(P,Q,R,S).
Implement the function F using an 8:1 multiplexer, without any
other logic gate. Only the constants 0 and 1, and the literals (but
not their complements) are available.
Fill in the inputs in the multiplexer diagram.
(b). Implement the function F
using a 24 decoder and a 4:1 multiplexer, and at most one logic
gate. Only the constants 0 and 1, and the literals (but not their
complements) are available....
Design the circuit for f(A,B,C,D)=ΠM(0,1,4,7,8,12-15),d(2,3,10) using a minimal number of 3-to-8 line decoders and NAND gates...
Design the circuit for f(A,B,C,D)=ΠM(0,1,4,7,8,12-15),d(2,3,10) using a minimal number of 3-to-8 line decoders and NAND gates (any size). Decoder outputs must be active-low. Also, assume that the decoder has one active-high enable line G0. If you need NOT gates, you must show them in the diagram using NAND gates.
Design the circuit with a 3-to-8 decoder and external OR gates. 8 Assume we want to implement a function: =Zm(1,2,6,7) (F(X,Y,Z You may label necessary parts of the diagrams with x, X, Y, Y', Z, Z', 1,0, F, etc.. a. Show how to implement the function F using only the decoder below and one additional gate. +5V Q7 EN Q6 Q5 Q4 Q악 Q1 SO
Create a minimal design for a 2-to-1 multiplexer using only NAND gates. Assume that no inverted input signals are available. Do not use any other type of gate. If you need to invert a signal, it must be done using a NAND gate.
3. [20 pts] 8-segment decoder for 8 symbols. Implement (draw logic diagram) the segment 4 of the 8-segment decoder for 8 symbols 0 (a) Using K-map to realize the function q 16 pts) (b) Using a 3-8 decoder and OR gates to realize the function q.[7 pts] (e Using 8-to-1 multiplexer to realize the function 17 pts] Notes: 1. A eight-segment decoder is a combinational circuit with a three-bit input a and a 8-bit output q. Each bit of q...
ECE 1552- Summer 2019 Homework 2: Solve all questions. HW is to be turned in as a PDF or word document on canvas. Show all working. Answers provided should be typed or written CLEARLY 1: Find a function to detect an error in the representation of a decimal digit in BCD. In other words, write an equation with value 1 when the inputs are any one of the six unused bit combinations in the BCD code, and value 0 otherwise...
Draw the schematic of a 2-4 line decoder using basic gates. (xou need to use 7404, 7408 & 7432. For detailed instruction about these ICs refer to Lab HO #3). 1. 2. Write down the IC numbers and pin numbers of the gates in your schematic. 3. Find the Truth Table and Boolean Expression of the circuit 4. 5. Now based on the same design principles comclude a 3-8 line decoder and draw the diagram only (no need for the...
Computer architecture
Having the next Boolean functions: F1(x,y,z)-П (1, 3, 5) . F2(x,y,z)-Σ (0, 2, 4, 5) . 1. Make one logic gate design circuit, using AND, OR and NOT logic gates (20 points). 2. Design two 4-to-1 selectors, one for each Boolean function (20 points) 3. Design one 3-to-8 decoder to solve both Boolean functions (20 points) 4. Design a 8x2 ROM to solve both Boolean functions (20 points) 5. Design a 3x5x2 PLA to solve both Boolean functions...
(a) The truth table below shows a certain function
F(P,Q,R,S).
Implement the function F using an 8:1 multiplexer, without any
other logic gate. Only the constants 0 and 1, and the literals (but
not their complements) are available.
Fill in the inputs in the multiplexer diagram.
(b). Implement the function F
using a 24 decoder and a 4:1 multiplexer, and at most one logic
gate. Only the constants 0 and 1, and the literals (but not their
complements) are available....
Most questions answered within 3 hours.
-
Question Three
Suppose you as project manager are using the Waterfall
development methodology on a large...
asked 40 minutes ago -
Which statement is not true about welfare in Canada?
A.Benefits typically vary based on one's ability...
asked 1 hour ago -
Please help me with FLOWCHART and UML diagram for class,
thank you!
#include <iostream>
#include <fstream>...
asked 1 hour ago -
3. Describe the “logic circuit” of the Lac operon. Which
proteins are bound or not to...
asked 1 hour ago -
Ayesha’s adjusted gross income is $60,000 in 2019. She donated a
piece of artwork with a...
asked 2 hours ago -
For Dijkstra’s shortest path algorithm:
a. Give the Big-O time for Dijkstra’s shortest path algorithm
and...
asked 2 hours ago -
Phosphorus violates the 'octet rule' in biological molecules,
forming more covalent bonds than expected based on...
asked 2 hours ago -
A 1.3 eV electron has a 10-4 probability of tunneling
through a 2.4 eV potential barrier....
asked 2 hours ago -
What is the one ingredient that is common to being successful
with all stakeholders?
profit
trust...
asked 2 hours ago -
Write an assembly language 32 bit program that reads in lines of
text by a .txt...
asked 2 hours ago -
what is the density ( in g/L) of hydrogen gas at 29 degrees C and a...
asked 2 hours ago -
5-6. You are considering three investment alternatives for some
spare cash: Old Reliable Corporation stock (A1),...
asked 2 hours ago