Question

Consider the execution of the program below on a fully bypassed (i.e. both W-E and M-E operand forwarding), 5-stage MIPS pipeline with early branch resolution (i.e., branches resolved in D stage).

i1: add $v0, $0, $0

i2: addi $t0, $0, 100

i3: lw $t1, 0($a0)

i4: add $v0, $v0, $t1

i5: addi $a0, $a0, 4

i6: addi $t0, $t0, -1

i7: beq $t0, $0, end

I8: beq $0, $0, i3

end:

Which lines in the program would require stalls based on data dependencies

Reorder the program so that no stalls are required.

Answer 1

• I4 instruction will need to stall for 1 clock cycle waiting for t1 (RAW)
• I7 instruction also will need to stall for 1 cycle waiting for t0 (RAW)

Reordering below will not cause any stall.

• i1: add $v0, $0, $0
• i3: lw $t1, 0($a0)
• i2: addi $t0, $0, 100
• i4: add $v0, $v0, $t1
• i6: addi $t0, $t0, -1
• i5: addi $a0, $a0, 4
• i7: beq $t0, $0, end
• I8: beq $0, $0, i3
• end