The code chain below is executed on a data forwarding, 5-stage pipelined processor. Which of the following instructions will encounter a stall? Write the instruction number along with the number of stall cycles that instruction experiences.
(Note the data forwarding)
1. add $4, $5, $6
2. add $7, $4, $5
3. sw $8, 0($7)
4. add $8, $8, $6
5. lw $6, 0($8)
6. add $10, $9, $8
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | ||
add $4, $5, $6 | IF | ID | EX | MEM | WB | $4 is forwarded at the end of 3rd clock cycle | |||||
add $7, $4, $5 | IF | ID | EX | MEM | WB | $7 is forwarded at the end of 4th clock cycle | |||||
sw $8, 0($7) | IF | ID | EX | MEM | WB | ||||||
add $8, $8, $6 | IF | ID | EX | MEM | WB | $8 is forwarded at the end of 6th clock cycle | |||||
lw $6, 0($8) | IF | ID | EX | MEM | WB | $6 is available at the end of 8th clock cycle | |||||
add $10, $9, $8 | IF | ID | EX | MEM | WB |
No instruction in the above code experience a stall cycle.
The code chain below is executed on a data forwarding, 5-stage pipelined processor. Which of the...
Computer architecture help: (60 points) The following instructions are executed on the 5-stage MIPS pipelined datapath. add r5,r2, r1 lw r3, 4(r5) lw r2, 0(r2) or r3, r5, r3 sw r3, 0(r5) (a) (20 points) List the data hazards in the above code. For each data hazard identified, clearly mark the source and the destination. For example you can say, there is a data hazard from instruction X to instruction Y on register Z. (b) (20 points) Assume there is...
Consider the following code to be executed on a pipelined processor lw $s1, 40(Ss6) add $s6, $s2, $s2 sw Ss6, 48(Ss1) a. Include stalls/nops in the code so it executes correctly in the cases of (i) No forwarding (ii) ALU-ALU for warding, (iii) Full forwarding b. In each case calculate the number of clock cycles required to execute the code c. Assume further that the clock cycle time is 110 ps with no forwarding, 120 ps with ALU-ALU forwarding and...
Given the following sequence of instructions to be executed on a 5-stage pipelined datapath as decrypted in our textbook: I1: add $8, $12,$10 12: SW $9,0 ($8) 13: lw $8,4($9) I4: and $12,$12,$8 15: SW $8,0($9) a. List true dependencies in the given sequence in the format of (register involved producer instruction, consumer instruction). Use labels to indicate instructions For example: ($0, I10, I11) means a true dependence between instruction I10 and I11: value of register $0 is generated by...
7 [24 marks] Consider the following MIPS code segment that is executed on a 5-stage pipeline architecture that does not implement forwarding or stalling in hardware. (1) add $4, $1, $1 (2) add $7, $4, $9 (3) lw $2, 40($8) (4) sub $8, $1, $2 (5) sw $8, 80(S2) (6) sub $2, $8, $4 (7) lw S8, 2($1) (8) add $8, $4, S2 Identify the data dependences that cause hazards. You are to use the following format to inform each...
In the class, we have shown how to maximize performance on our pipelined datapath with forwarding and stalls on a use following a load. Rewrite the following code to minimize performance on this datapath – that is, reorder the instructions so that this sequence takes the most clock cycles to execute while still obtaining the same result: lw $3, 0($5) lw $4, 4($5) add $7, $7, $3 add $8, $8, $4 add $10, $7, $8 sw $6, 0($5) beq $10,...
1. Given the following instruction sequence for the MIPS processor with the standard 5 stage pipeline $10, S0. 4 addi lw S2.0(S10) add sw S2,4(510) $2, $2, $2 Show the data dependences between the instructions above by drawing arrows between dependent instructions (only show true/data dependencies). a. Assuming forwarding support, in what cycle would the store instruction write back to memory? Show the cycle by cycle execution of the instructions as they execute in the pipeline. Also, show any stalls...
These two pieces of code are executed on a 5 stage pipelined processor. Code-A : Counting sum of 1 to 100 using a for loop . Code-B : Looping through 100 values and printing if values are +ve or -ve. There is 50-50 chance of value being positive or negative. This processor always predicts 'branch is taken'. Which code does suffer more from purging / aborting instruction on fly? a) Both will suffer equal b) Insufficient information c) Code A ...
I just need part (d) answered 7) [24 marks] Consider the following MIPS code segment that is executed on a 5-stage pipeline architecture that does not implement forwarding or stalling in hardware. (1) add $4, $1, $1 (2) add $7, $4, $9 (3) lw $2, 400S8) (4) sub $8, $1, $2 (5) SKSs, so($2) (6) sub $2, $8, $4 (7) lw $3, 2($1) (8) add $8, $4, $2 Identify the data dependences that cause hazards. You are to use the...
a).For the following MIPS assembly code to be executed using the pipelined datapath, identify all of the data dependencies (which register in which instruction needs the result register value from which another instruction?) and enumerate them (give them numbers as 1,2, ...). b).Which dependencies are data hazards that will be resolved via forwarding and without a stall (you can specify the number(s) from the part a)? c).Which dependencies are data hazards that will cause a stall (you can specify the...
2 This exercise is intended to help you understand the relationship between forwarding hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a 5-stage pipelined datapath: lw r5,4(r5) add r5,r2,r5 Iw r3,0(r5) or r3,r5,r3 sw r4,0(r5) 2.1 If there is no forwarding or hazard detection, how many nops needed to be inserted to ensure correct execution, and how many cycles needed to execute the codes? 2.2...