Question

• Why can you not have large TTL fan-out from the output of a CMOS device?

Answer 1

Solution -first of all we have to know what is the TTL fan- out and CMOS device

TTL faimly - the ttl faimly was the most widely used logic faimy for several year chareacterised by its relitivity high speed operation ,it has now been largely repaced by cmos logic the physical represntation of tge binary logic states in these faimilies are high and low voltage.

TTL CHARACTERISTICS - each logic faimly is characterised by several important parameter these properties and how the reletated to the TTL logic faimly.

FAN-OUT - fan-out specifies the no. of statndered loads that the output of the gate can drive without impairing of its noramal operation.

due to the nature of TTL gate, two different fanout values are given , one for high outpit and one for low output.

CMOS FAIMLY - cmos ogic is examlified by its extremely low poer conspution and high noise immunity,

hence its prevalently used in device demanding low power dissipation such as digital wristwatches and other bettery power device or in devie oprate in noisy envionrment such as industrial plant.

A wide variety of CMOS logic devicein the 4000 series are available

CMOS CHARACTERSTICS

The voltage transfer curve for a typically CMOS logic gate, the curve in the transition region are almost vertical this narrow transition region is reason for CMOS logic high noise immunity, not much voltage range is covered in th etransition form one state to other. to conrtast to TTL device the thjresold voltage depends on the supply voltage.

The main reason we dont used the large TTL fan out from the output of CMOS device

-The fan out of CMOS device is usually graeter than 50 beacouse the input current requirment of CMOS logic is nil (pA). however, current is requird to charge discharge the capacitance of CMOS inputs during logic transition.hence the greater the fan out the longer the propagation dealy.

e.g. with VDD=5V, the propagation delay will increased from 60nsec when the out drive 1 input to 50nsec whrn the output drive 10 inputs. as rule of thumb you can assume the load will be 5 pf per CMOS input 5 to 15 pf for stay wiring capacitance.

outputs of cmos gates like those of totem-pole TTL gate , should never be connected togather also, the power supply should be turned on before applying any logic signal to CMOS device and the logic signal should be removed before turning off the supplly , other wise the device could be damaged.