Question

Please design a circuit that outputs two 3-bit’s multiplication results in Signed 2's complement system

(the sign+- and magnitude of the multiplication result output separately)

Answer 1

Solution:

The multiplication of binary arguments expressed as sums of products of bit values and weights of positions in the 2's complement representation can be transformed, through appropriate term grouping and introduction of bit complements, to the form, which is a basis for constructing an array multiplier composed of elementary adders. In the array of elementary adders so many rows appear how many bits are in the number that are multiplied.

On the inputs of the initial layer of elementary adders and to carry inputs at lower levels, appropriate logical products are supplied of multiplicand and multiplier bits (by AND operation). The results of elementary additions (sum and carry bits) are supplied on inputs of adders in particular lower layers or they constitute already result bits, depending on the position of a given adder in the array.

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