Design the circuit specified by Table and use the sequence from Problem (either yours or the one posted on the text website) to perform an automatic logic simulation-based verification of your design.
TABLE State Table for Circuit of Problem
Present State | Inputs | Next State | Output | |||
A | B | X | Y | A | B | Z |
0 | 0 | 0 | 0 | 1 | 0 | 0 |
0 | 0 | 0 | 1 | 1 | 1 | 1 |
0 | 0 | 1 | 0 | 1 | 1 | 0 |
0 | 0 | 1 | 1 | 1 | 1 | 1 |
0 | 1 | 0 | 0 | 0 | 1 | 1 |
0 | 1 | 0 | 1 | 0 | 0 | 0 |
0 | 1 | 1 | 0 | 0 | 0 | 1 |
0 | 1 | 1 | 1 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 1 | 1 |
1 | 0 | 1 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 1 | 1 | 0 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 |
1 | 1 | 1 | 1 | 1 | 1 | 1 |
Problem
The plus (+) indicates a more advanced problem and the asterisk (*) indicates thata solution is available on the Companion Website for the text.
*Generate a verification sequence for the circuit described by the state table in Table. To reduce the length of the simulation sequence, assume that the simulator can handle X inputs and use X’s whenever possible. Assume that a Reset input is available to initialize the state to A = 0, B = 0 and that all transitions in the state diagram must be exercised.
Problem
The plus (+) indicates a more advanced problem and the asterisk (*) indicates thata solution is available on the Companion Website for the text.
*Generate a verification sequence for the circuit described by the state table in Table. To reduce the length of the simulation sequence, assume that the simulator can handle X inputs and use X’s whenever possible. Assume that a Reset input is available to initialize the state to A = 0, B = 0 and that all transitions in the state diagram must be exercised.
TABLE State Table for Circuit of Problem
Present State | Inputs | Next State | Output | |||
A | B | X | Y | A | B | Z |
0 | 0 | 0 | 0 | 1 | 0 | 0 |
0 | 0 | 0 | 1 | 1 | 1 | 1 |
0 | 0 | 1 | 0 | 1 | 1 | 0 |
0 | 0 | 1 | 1 | 1 | 1 | 1 |
0 | 1 | 0 | 0 | 0 | 1 | 1 |
0 | 1 | 0 | 1 | 0 | 0 | 0 |
0 | 1 | 1 | 0 | 0 | 0 | 1 |
0 | 1 | 1 | 1 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 1 | 1 |
1 | 0 | 1 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 1 | 1 | 0 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 |
1 | 1 | 1 | 1 | 1 | 1 | 1 |
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