Write a gate-level structural VHDL description for the circuit from Problem. Use the VHDL...

Write a gate-level structural VHDL description for the circuit from Problem. Use the VHDL model for a D flip-flop from Figure. Use the package func_prims in library lcdf_vhdl for the logic gate components.

Figure VHDL Process Description of Positive-Edge-Triggered Flip-Flop with Reset

Problem

A sequential circuit has two D flip-flops, one input X, and one output Y. The logic diagram of the circuit is shown in Figure. Derive the state table and state diagram of the circuit.

Figure Circuit for Problem