Write a gate-level structural Verilog description for the circuit from Problem. Use the Ve...

Write a gate-level structural Verilog description for the circuit from Problem. Use the Verilog model for a D flip-flop from Figure.

Figure Verilog Process Description of Positive-Edge-Triggered Flip-Flop with Reset

Problem

A sequential circuit has two D flip-flops, one input X, and one output Y. The logic diagram of the circuit is shown in Figure. Derive the state table and state diagram of the circuit.

Figure Circuit for Problem