The plus (+) indicates a more advanced problem and the asterisk (*) indicates thata soluti...

The plus (+) indicates a more advanced problem and the asterisk (*) indicates thata solution is available on the Companion Website for the text.

*A serial 2s complementer is to be designed. A binary integer of arbitrary length is presented to the serial 2s complementer, least significant bit first, on input X. When a given bit is presented on input X, the corresponding output bit is to appear during the same clock cycle on output Z. To indicate that a sequence is complete and that the circuit is to be initialized to receive another sequence, input Y becomes 1 for one clock cycle. Otherwise, Y is 0.

(a) Find the state diagram for the serial 2s complementer.

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(b) Find the state table for the serial 2s complementer.

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(c) Write an HDL description for the state machine for the odd parity generator using Example 1 (VHDL) or Example 4-15 (Verilog) as a template.

Example 1 VHDL for the Sequence Recognizer

Example 2 Verilog for the Sequence Recognizer