Write a gate-level HDL description of the circuit from Problem including delays for each c...

Write a gate-level HDL description of the circuit from Problem including delays for each component. Show that the circuit operates incorrectly when operated at a frequency greater than the maximum frequency you found as your answer for Problem.

Problem

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*A sequential circuit is shown in Figure. The timing parameters for the gates and flip-flops are as follows:

(a) Find the longest path delay from an external circuit input passing through gates only to an external circuit output.

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(b) Find the longest path delay in the circuit from an external input to positive clock edge.

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(c) Find the longest path delay from positive clock edge to output.

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(d) Find the longest path delay from positive clock edge to positive clock edge.

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(e) Determine the maximum frequency of operation of the circuit in megahertz (MHz).

Figure Circuit for Problem