(Word Problem) Design a state diagram to perform the following function. There are two dat...

(Word Problem) Design a state diagram to perform the following function. There are two data inputs A and B, a check input C, and an output D. The FSM takes as input two continuous, synchronous streams of 4-bit twos-complement numbers in a bit-serial form with the most significant (sign) bit first. The least significant bit is marked by a 1 on the check line (C). During the time slot in which C is asserted, the output D should go to a 1 if the twos-complement number on A is larger than the twos- complement number on B.

(a) Complete the timing diagram in Figure 1 to make sure you fully understand the statement of the problem.

---

(b) Draw a state diagram that implements this specification using as few states as possible. (Hint: It is possible to implement this machine in six or fewer states.)

Figure 1

Timing diagram for serial number comparator.