(Interfacing Memories) In this exercise, you will design a memory- controller finite state...

(Interfacing Memories) In this exercise, you will design a memory- controller finite state machine that implements a processor- memory handshake to the following specification. The processor initiates a transfer request by asserting REQ (request) while specifying a Read or Write (RW) operation. During a Read operation (RW asserted), the processor waits for the memory controller to assert (Data Available). The processor can then sample the data. It unasserts the REQ line to end the memory cycle. During a write operation (RW unasserted), the processor drives data to the memory system, waiting for the memory controller to assert (Write Complete). When the processor sees this, it unasserts REQ to end the cycle. This is a variation of the four-cycle handshake described in Chapter 4.

The Moore state diagram for the memory controller is shown in Figure 1a). Note that the read and write require multiple states for their execution. A timing diagram, showing the relationships between the critical control signals for a read and a write cycle, is given in Figure 1(b). The state control- signal outputs are listed in Figure 1(c). Several of the memory controller’s signals listed here are used to control the memory components. Their detailed meaning is not important, except that the appropriate signals should be asserted in the listed states.

(a) Choose a good state assignment and implement using discrete gates and flip-flops. What kind of PAL would you need to implement this machine in a single chip (in particular, number of inputs/outputs, flip-flops, product terms per output, etc.)?

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(b) How many Xilinx CLBs would it take to implement your solution to part (a)? Justify your answer.

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(c) Implement the state machine using a four-bit counter as a state register. Show your counter-based state assignment, and your implementation of the next-state function in terms of clear, count, and load. What kind of PAL would you need to implement the next state control in a single chip. (Hint: Assume the state register is implemented externally with a 163 synchronous up-counter).

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(d) How many Xilinx CLBs would it take to implement your solution to part (c), including the counter state register and the output logic?

Figure 1

Memory controller.