(Word Problem) You are to design a finite state machine to control the position of a mechanical arm. Your inputs include two registers, R0 and R1, that contain the current position of the arm and the target position, respectively, encoded as 32-bit twos- complement numbers. R0 automatically is updated by external logic on every clock pulse.
The machine should operate as follows. The FSM commences operation when a Start pulse is asserted. If the current position is less than the target, the machine should assert a Forward signal. If the position is greater than the target, a Reverse signal should be asserted. If the position is already correct, return to the initial off state. When the arm has moved seven eighths of the way to the target from its initial position, an additional Slow output should be activated to brake the motion of the arm. You may assume that the arm moves slowly enough with respect to your FSM’s clock rate that you need not worry about overshooting the target.
You will probably need additional data-path objects besides registers R0 and R1. Draw a register diagram of your data path, showing the elements and how they are interconnected. Then draw the controller’s state diagram, showing the high-level register transfer operations that are asserted in each state or transition (you may choose Moore or Mealy implementation, at your own discretion).
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