For the circuit shown in Fig. P4.1, (a) Write and verify a gate-level HDL model of the...

For the circuit shown in Fig. P4.1,

(a) Write and verify a gate-level HDL model of the circuit.

(b) Compare your results with those obtained for Problem 4.1.

Reference: Problem 4.1

Consider the combinational circuit shown in Fig. P4.1 . (HDL—see Problem 4.49.)

(a) Derive the Boolean expressions for T₁ through T₄. Evaluate the outputs F₁ and F₂ as a function of the four inputs.

(b) List the truth table with 16 binary combinations of the four input variables. Then list the binary values for T₁ through T₄ and outputs F₁ and F₂ in the table.

(c) Plot the output Boolean functions obtained in part (b) on maps and show that the simplified Boolean expressions are equivalent to the ones obtained in part (a).