Develop and modify the eight-bit ALU specified in Problem 4.44 so that it has three-state output controlled by an enable input, En . Write a test bench and simulate the circuit.
Reference: Problem 4.44
Using a case statement, write an HDL behavioral description of a eight-bit arithmeticlogic unit (ALU). The circuit has a three-bit select bus (Sel), sixteen-bit input datapaths (A[15:0] and B[15:0]), an eight-bit output datapath (y[15:0]), and performs the arithmetic and logic operations listed below.
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