Using a continuous assignment, develop and simulate a dataflow model of
(a) The four-bit incrementer described in Problem 4.11(a).
(b) The four-bit decrementer described in Problem 4.11(b).
Reference: Problem 4.11
Using four half-adders (HDL—see Problem 4.52),
(a) Design a full-subtractor circuit incrementer. (A circuit that adds one to a four-bit binary number.)
(b) Design a four-bit combinational decrementer (a circuit that subtracts 1 from a four-bit binary number).
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