9.7 Consider the following CMOS logic circuit which is a simple domino circuit. Node X is...

9.7 Consider the following CMOS logic circuit which is a simple domino circuit. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the domino circuit.

(a) Explain how the voltage level at node X, after it is precharged to 5 V, can be affected by the charge sharing between node X and node Y if their node capacitances are the same. Express the final voltage at node X in terms of the initial voltage at node Y when the charge sharing is completed following the full precharge operation when the gate terminal of M2 transistor is fixed at 0 V.

(b) Determine the ratio between device transconductance parameters, k_p and k_n, of the inverter to prevent any logic error due to charge sharing between nodes X and Y under all circumstances. Assume that the magnitudes of threshold voltages in the inverter are equal to 1.0 V. The use of Level 1 transistor current equations is deemed adequate.

Figure P9.7