9.6 The inputs to a domino logic gate are always LO during precharge (ϕ = LO) and may unde...

9.6 The inputs to a domino logic gate are always LO during precharge (ϕ = LO) and may undergo a LO-to-HI transition during evaluate (ϕ = HI). Consider the domino 3-input AND gate shown in Fig. P9.6 below. If, during evaluate, A = HI, B = LO, and C = LO, charge sharing will cause the voltage at the input of the inverter to drop. Given that the switching threshold of the inverter is 3V, calculate the maximum ratio C_p/C_L needed to ensure that charge sharing does not corrupt the value of F for the given case.

Figure P9.6