9.1 Consider the CMOS circuit shown in Fig. P9.1 that was designed to drive a total capaci...

9.1 Consider the CMOS circuit shown in Fig. P9.1 that was designed to drive a total capacitive load of C_L = 0.2 pF. For the n-channel devices, assume zero bias threshold voltage V_T0 = 1.0V and transconductance parameter k′_n= 50 μA/V². For the p-channel devices, assume V_T0 = -1.0 V and k′_p = 25 μA/V². For all the devices, assume the W/L ratios for each device is shown in the figure. The initial voltage across the load capacitor C_L is 0 V. The waveform at input E is identically 0V for all time. For the clock CK and the rest of the inputs, the waveforms are also shown in the figure. Sketch the voltage waveform across the load capacitor C_L and provide clear marking of the 50% crossings along the time axis in nanoseconds for both rise and fall transitions. [Hint: The n-channel transistor group can be approximated by a single equivalent n-channel transistor and either an average current method or a state equation method may be used to compute the required delay times.

Figure P9.1